rv64im_min_uart.nx

rv64im_min_uart.nx -- 16550-compatible UART MMIO device. The kernel's only observable output channel. Without this, no "[m0-mcs-live]" marker prints, no bench output reaches the host, nothing about the kernel's run is visible. Tier A FPGA bring-up exit criterion #2 from rv64im_min_target_spec.md depends on this module producing the QEMU-reference selftest output. Tier A scope: TX-only, polled (no RX, no FIFO, no interrupts). Kernel never reads stdin and uses busy-wait on LSR.THRE between bytes (uart.nx:38-41); the kernel's MIE-masking-for-atomicity pattern still works because nothing else generates interrupts during a write. Memory map (matches QEMU virt machine; kernel hardcodes 0x10000000): 0x10000000 THR (offset 0) TX holding register; 8-bit write 0x10000001..4 unused; reads return 0 0x10000005 LSR (offset 5) Line status; bit 5 = THRE 0x10000006.. reads return 0 LSR bit semantics (subset relevant to kernel): bit 0: DR (data ready -- not used, RX absent) bit 5: THRE (TX holding empty -- always 1 in Tier A; no FIFO) bit 6: TEMT (TX empty -- always 1; alias of THRE for this device) Status: SEED. 2026-05-26. Register storage + TX byte sink (host stdout for simulator; real UART line for FPGA bitstream).