nx_rv64_atomic_gate.nx

nx_rv64_atomic_gate.nx -- LN34 REFEREE (lang.plan): the IR atomic family on the rv64 lane, from the byte up. ONE FAMILY, THREE LOWERINGS: __atomic_load/store/cas/faa_i64 + __atomic_fence (nx_atom.nx wraps them) lower to OP_ATOMIC_* in the IR; x86-64 lowers those to LOCK instructions (pre-existing), the wasm lane to the 0xFE family (nx_wasm_threads_gate), and -- proven HERE -- the rv64 backend (nx_riscv.nx) to RV64A: amoadd.d.aqrl, an lr.d/sc.d.aqrl compare-and-swap loop, and the ISA manual's sequentially-consistent fence mappings. FOUR LEGS, each composed IN-PROCESS so nothing is trusted by name: A. the sovereign text assembler (nx_rv64_asm) encodes every new mnemonic to the word an independent field-layout encoder predicts (funct5<<27 | aq<<26 | rl<<25 | rs2<<20 | rs1<<15 | funct3<<12 | rd<<7 | 0x2F; fence = pred<<24 | succ<<20 | 0x0F), refuses a malformed fence, and now admits `.L<name>:` labels while still skipping `.globl`-style directives; B. the behavioural sim (rv64im_min_sim, the same instance the A-extension conformance gate drives) executes the assembled program with the hand-computed register and memory results; C. the compiler backend, driven exactly as nx_nxc drives it (lex -> parse -> opt -> regalloc -> emit_function), lowers a fixture carrying every atomic op to those mnemonics and leaves no `# unhandled op`, while a plain fixture carries none of them (the neutrality neg-control); D. END TO END: the backend's emitted `tick` function is assembled by leg A's assembler and RUN on leg B's sim with a0/a1 as arguments and ra pointing at a self-loop sentinel, and the sim's a0 equals the tick count. nx_rv64_atomic_gate license_tier: ORIGINAL No hw writes (Rule 26).