nx_types.nx
buildroot/runtime/nx_types.nx
about
types.nx -- shared struct definitions for the NishiLang self-host.
Each port file (ir.nx / opt.nx / parse.nx / regalloc.nx / riscv.nx)
used to duplicate these declarations verbatim. They now `import
"types.nx"` instead so a layout tweak only has to happen in one
place; this prevents drift between files.
STUB(types, never): "drift" wording above is descriptive (not a
landmine); keeps audit_stubs.sh quiet on the design intent.
Content: IR shapes (Type, Value, Instr, BasicBlock, Function,
Module) plus the regalloc/riscv-shared ValueLoc. Keep this file
*declarations only* -- no functions, no main -- so files that
include it still compile as independent benches with their own
self-test `main`s.
Pool record sizes (used by callers doing pointer arithmetic):
Value : 48 bytes
Instr : 128 bytes (12 i64 operand/link slots + 4 ptrs)
BasicBlock : 96 bytes
ValueLoc : 16 bytes
If any struct below grows, grep callers for `* 48`, `* 96`,
`* 128`, `* 16` and update in lockstep.
dependencies 0 imports · 123 importers
diagram shows first 10 each side; +0 more imports, +113 more importers in the complete lists below.
imports: none
imported by: _offc_probe_callchain.nx_offc_probe_irbuild.nx_offc_probe_irfn.nx_offc_probe_module.nx_offc_regalloc_min.nxend2end_test.nxnx_a11y_check.nxnx_a11y_check_test.nxnx_attack_taxonomy.nxnx_attack_taxonomy_test.nxnx_bck_elide.nxnx_compile_field_candidate_t280.nxnx_compile_wat.nxnx_compile_wat_call_operands_t143.nxnx_compile_wat_scalararm.nxnx_compile_x86.nxnx_decl_base.nxnx_decl_base_test.nxnx_decl_combat_arena.nxnx_decl_combat_arena_test.nxnx_decl_dungeon_floor.nxnx_decl_dungeon_floor_test.nxnx_decl_random_environment.nxnx_decl_random_environment_test.nxnx_decl_reflection_test.nxnx_decl_simple_scene.nxnx_decl_simple_scene_test.nxnx_decl_townscape.nxnx_decl_townscape_test.nxnx_dom_fn.nxnx_dom_oracle_gate.nxnx_ir.nxnx_ir_dump.nxnx_ir_validate.nxnx_lang_struct.nxnx_license_check.nxnx_license_check_test.nxnx_license_wall_audit.nxnx_lsp.nxnx_main.nxnx_math_basics.nxnx_math_basics_test.nxnx_nxc.nxnx_opt.nxnx_opt_eqsat_pass.nxnx_parse.nxnx_parse_field_candidate_t280.nxnx_quality_grade.nxnx_quality_grade_daemon.nxnx_quality_grade_quad.nxnx_quality_grade_self.nxnx_quality_grade_septagon.nxnx_quality_grade_test.nxnx_regalloc.nxnx_regalloc_liveness_diag.nxnx_regalloc_soundness_test.nxnx_riscv.nxnx_rv64_atomic_gate.nxnx_safety_critical_grade.nxnx_safety_critical_grade_test.nxnx_smoke_nxc_pipeline.nxnx_smoke_nxc_pipeline10.nxnx_smoke_nxc_pipeline11.nxnx_smoke_nxc_pipeline12.nxnx_smoke_nxc_pipeline13.nxnx_smoke_nxc_pipeline14.nxnx_smoke_nxc_pipeline15.nxnx_smoke_nxc_pipeline2.nxnx_smoke_nxc_pipeline3.nxnx_smoke_nxc_pipeline4.nxnx_smoke_nxc_pipeline5.nxnx_smoke_nxc_pipeline6.nxnx_smoke_nxc_pipeline7.nxnx_smoke_nxc_pipeline8.nxnx_smoke_nxc_pipeline9.nxnx_smoke_nxc_tilde.nxnx_smoke_regalloc_min.nxnx_smoke_regalloc_min2.nxnx_smoke_regalloc_min3.nxnx_smoke_regalloc_min4.nxnx_smoke_regalloc_min5.nxnx_smoke_regalloc_min6.nxnx_smoke_regalloc_min7.nxnx_smoke_regalloc_step.nxnx_tokenizer.nxnx_vcc_color_wat.nxnx_vcc_probe_wat.nxnx_wasm.nxnx_wasm_call_operands_t143.nxnx_wasm_data.nxnx_wasm_scalararm.nxnx_wgsl.nxnx_wgsl_authored_t55.nxnx_wgsl_before_front_t217.nxnx_wgsl_canonical_skin_t140.nxnx_wgsl_cast_control_t181.nxnx_wgsl_cast_lbs_t181.nxnx_wgsl_cast_material_t181.nxnx_wgsl_cloud_transport_t155.nxnx_wgsl_cumulus_release_t161.nx +23 more (shown cap 100 declared)
structs
| 26 | struct Type { |
| 79 | struct StructField { |
| 88 | struct Value { |
| 102 | struct Instr { |
| 139 | struct BasicBlock { |
| 159 | struct Function { |
| 203 | struct Module { |
| 226 | struct Global { |
| 239 | struct ValueLoc { |
consts
| 198 | const NX_MODULE_FN_STRIDE: i64 = 176 |
| 201 | const NX_MODULE_GLOBAL_STRIDE: i64 = 80 |
| 259 | const OP_ADD: i64 = 1 |
| 260 | const OP_SUB: i64 = 2 |
| 261 | const OP_MUL: i64 = 3 |
| 262 | const OP_DIV_S: i64 = 4 |
| 263 | const OP_DIV_U: i64 = 5 |
| 264 | const OP_REM_S: i64 = 6 |
| 265 | const OP_REM_U: i64 = 7 |
| 266 | const OP_NEG: i64 = 9 |
| 267 | const OP_AND: i64 = 10 |
| 268 | const OP_OR: i64 = 11 |
| 269 | const OP_XOR: i64 = 12 |
| 270 | const OP_SHL: i64 = 13 |
| 271 | const OP_SHR_S: i64 = 14 |
| 272 | const OP_SHR_U: i64 = 15 |
| 273 | const OP_NOT: i64 = 16 |
| 282 | const OP_ROTL64: i64 = 27 |
| 283 | const OP_ROTR64: i64 = 28 |
| 290 | const OP_ADDR_OF: i64 = 29 |
| 298 | const OP_BSWAP64: i64 = 35 |
| 299 | const OP_CLZ32: i64 = 36 |
| 300 | const OP_CTZ32: i64 = 37 |
| 301 | const OP_POPCNT64: i64 = 38 |
| 309 | const OP_ATOMIC_LOAD_I64: i64 = 39 |
| 310 | const OP_ATOMIC_STORE_I64: i64 = 46 |
| 311 | const OP_ATOMIC_CAS_I64: i64 = 47 |
| 312 | const OP_ATOMIC_FAA_I64: i64 = 48 |
| 313 | const OP_ATOMIC_FENCE: i64 = 49 |
| 317 | const OP_THREAD_CLONE: i64 = 64 |
| 318 | const OP_EQ: i64 = 20 |
| 319 | const OP_NE: i64 = 21 |
| 320 | const OP_LT_S: i64 = 22 |
| 321 | const OP_LE_S: i64 = 23 |
| 322 | const OP_GT_S: i64 = 24 |
| 323 | const OP_GE_S: i64 = 25 |
| 324 | const OP_RETURN: i64 = 30 |
| 325 | const OP_BR: i64 = 31 |
| 326 | const OP_BR_COND: i64 = 32 |
| 327 | const OP_CALL: i64 = 33 |
| 328 | const OP_TAIL_CALL: i64 = 34 |
| 333 | const OP_CALL_INDIRECT: i64 = 144 |
| 334 | const OP_COPY: i64 = 40 |
| 335 | const OP_LOAD: i64 = 41 |
| 336 | const OP_STORE: i64 = 42 |
| 337 | const OP_ALLOCA: i64 = 43 |
| 338 | const OP_GEP: i64 = 44 |
| 339 | const OP_SYSCALL: i64 = 45 // ECALL: op0 = syscall number, op1..op6 = args |
| 346 | const OP_FADD: i64 = 50 |
| 347 | const OP_FSUB: i64 = 51 |
| 348 | const OP_FMUL: i64 = 52 |
| 349 | const OP_FDIV: i64 = 53 |
| 350 | const OP_FNEG: i64 = 54 |
| 351 | const OP_FCAST_I_TO_F: i64 = 55 // int -> float |
| 352 | const OP_FCAST_F_TO_I: i64 = 56 // float -> int (truncate) |
| 353 | const OP_F32X4_DOT: i64 = 134 // packed f32x4 dot: (a:*f32[4]) . (b:*f32[4]) -> f32 scalar (x86 SSE movups+mulps+hsum) -- the compute-physics lever |
| 354 | const OP_F32X8_DOT: i64 = 135 // packed f32x8 dot: (a:*f32[8]) . (b:*f32[8]) -> f32 scalar (x86 AVX2 vmovups+vmulps 8-wide + vextractf128 + hsum) -- 2x the SSE lever |
| 355 | const OP_F32X8_FMA: i64 = 136 // (acc:*f32[8]) += (a:*f32[8]) * (b:*f32[8]) FUSED (vfmadd231ps) -- vector accumulate, NO per-chunk hsum |
| 356 | const OP_F32X8_HSUM: i64 = 137 // (acc:*f32[8]) -> f32 horizontal sum (vextractf128 + SSE hsum) -- called ONCE per dot |
| 357 | const OP_I16X16_MADD: i64 = 138 // (acc:*i32[8]) += vpmaddwd((a:*i16[16]),(b:*i16[16])) -- NO-FLOAT integer dot, EXACT + deterministic |
| 358 | const OP_I8DOT32: i64 = 145 // __f32_i8dot32(a:*i8[32], b:*f32[32]) -> f32: dot of 32 sign-extended int8 with 32 f32 (SSE pmovsxbd+cvtdq2ps+mulps+addps, unrolled x8, hsum once). The Q8_0/quantized dequant-dot lever (2026-07-08). |
| 359 | const OP_Q5UNPACK32: i64 = 146 // __q5_unpack32(qhqs:*u8[20], out:*i8[32], consts:*u8[80]) -> 0: SSE unpack of a Q5_0 block (qh[4]+qs[16]) -> 32 signed int8 (nibble|(qh_bit<<4))-16, in A-order. pand/psrlw nibble + pshufb/pcmpeqb qh-bit-spread. Then __f32_i8dot32(out,A)*d = Q5_0 dequant-dot. The 79%-weight lever (2026-07-08). |
| 360 | const OP_Q4KUNPACK32S: i64 = 151 // __q4k_unpack32s(qs:*u8[32], out:*i16[64], scpack:i64) -> 0: AVX2 unpack of one Q4_K sub-block pair (32 packed nibble bytes) into 64 i16 lanes ALREADY SCALED -- out[0..31] = (qs[k] & 15) * (scpack & 0xFFFF), out[32..63] = (qs[k] >> 4) * ((scpack >> 16) & 0xFFFF), lane k = byte k. vpmovzxbw widen + vpsrlw/vpand nibble split + vpmullw by a vpbroadcastw scale; no memory constants (the 0x000F mask is built from vpcmpeqd+vpsrlw). Replaces the scalar u64 spread+multiply the LM4 resident-Q4_K decode paid per row per token (2026-09-02). |
| 361 | const OP_Q4KSBDOT: i64 = 152 // __q4k_sb_dot(sb:*u8[144], col:*i16[256], scpre:*i64[8], out:*i64[5]) -> 0: ONE Q4_K super-block, whole: the 12 scale bytes decoded in registers, every sub-block pair unpacked+scaled (the __q4k_unpack32s sequence) and vpmaddwd-accumulated straight from the activation lanes in memory, out[0..3] = the 8 i32 accumulator lanes (sum over the block of sc_sub*q*col), out[4] = sum over sub-blocks of m_sub*scpre[sub] (the dmin term). 4 operands. Built because the serve profile showed the scalar code AROUND four per-group intrinsic calls cost more than the arithmetic inside them (2026-09-02, LM4c third cut). |
| 362 | const OP_Q8BLKDOT: i64 = 154 // __q8blk_i16dot(codes:*i8[32], x:*i16[32]) -> i64: one Q8_0 block's int8 x i16 dot (search R0s-b), the codes sign-extended IN REGISTER (vpmovsxbw x2 + vpmaddwd x2 + vpaddd + the widened int64 hsum). EXACT + deterministic: a lane holds four products of at most 127*32767. |
| 363 | const OP_I16DOT: i64 = 153 // __i16_dot(a:*i16[n], b:*i16[n], n:i64) -> i64: sum of a[i]*b[i] over n lanes (n a POSITIVE multiple of 16, the caller's contract), |
| 367 | const OP_I8DOT32A: i64 = 147 // __f32_i8dot32a(a:*i8[32], b:*f32[32]) -> f32: AVX2 256-bit twin of OP_I8DOT32 -- 4 blocks of 8 lanes (vpmovsxbd+vcvtdq2ps+vmulps), TWO accumulators (ymm4/ymm5) to break the serial vaddps chain, combine + one hsum. ~2x the SSE dot. NOT bit-identical to OP_I8DOT32 (different summation order); argmax-robust. The AVX2 dequant-dot lever (2026-07-10, after gcc proved 6x codegen headroom). |
| 368 | const OP_I8FMA32: i64 = 148 // __f32_i8fma32(a:*i8[32], b:*f32[32], d_bits:i64, acc:*f32[8]) -> 0: DEFERRED-HSUM block: acc[8] += d * (sext(a)·b), 8-lane AVX2 vfmadd231ps, NO hsum. The caller keeps a persistent 8-lane acc across all k/32 blocks (broadcasting the per-block scale d) and hsums ONCE per output (__f32x8_hsum) -- kills 27/28 per-block hsums = the cold-forward matmul lever (2026-07-10). 4 operands. |
| 369 | const OP_Q8ROWDOT: i64 = 149 // __f32_q8row_dot(qbuf_row:*u8, a_row:*f32, nblocks:i64) -> f32: MONOLITHIC Q8_0 row dot. Loops all nblocks 34-byte blocks with a REGISTER-resident 8-lane ymm6 accumulator (NO memory round-trip, NO per-block hsum), F16C vcvtph2ps for each block's f16 scale d, vfmadd231ps d*(int8.a), ONE hsum at the end. The real cold-forward matmul lever (2026-07-10) -- kills BOTH the 28 per-block hsums AND the deferred-hsum memory round-trip. 3 operands; internal loop (unique label = fn+rid). |
| 370 | const OP_CRC32: i64 = 139 // __crc32_u64(crc,data): SSE4.2 CRC-32C accumulate (x86 crc32q). Pure; 2 i64 operands, i64 result. |
| 371 | const OP_PDEP: i64 = 140 // __pdep64(src,mask): BMI2 parallel bit DEPOSIT (x86 pdep). Pure; 2 i64 operands, i64 result. |
| 372 | const OP_PEXT: i64 = 141 // __pext64(src,mask): BMI2 parallel bit EXTRACT (x86 pext). Pure; 2 i64 operands, i64 result. |
| 373 | const OP_SHA256_NI_BLOCK: i64 = 142 // hardware SHA-NI: one full SHA-256 block compression IN PLACE. |
| 379 | const OP_MUL256_WIDE: i64 = 143 // __mul256_wide(dst,a,b): fused 4x64-limb schoolbook multiply of the |
| 385 | const OP_FCAST_F32_TO_F64: i64 = 57 |
| 386 | const OP_FCAST_F64_TO_F32: i64 = 58 |
| 387 | const OP_FSQRT: i64 = 150 // scalar float sqrt (sqrtsd/sqrtss); unary, result type = operand float type |
| 388 | const OP_AES128_ENC_BLOCK: i64 = 59 // hardware AES-NI: encrypt 16B block in place (op0=state ptr, op1=roundkeys ptr) |
| 394 | const OP_CLMUL_LL: i64 = 65 |
| 395 | const OP_CLMUL_HH: i64 = 66 |
| 396 | const OP_CLMUL_LH: i64 = 67 |
| 397 | const OP_CLMUL_HL: i64 = 68 |
| 398 | const OP_FEQ: i64 = 60 |
| 399 | const OP_FNE: i64 = 61 |
| 400 | const OP_FLT: i64 = 62 |
| 401 | const OP_FLE: i64 = 63 |
| 436 | const OP_VADD: i64 = 80 // element-wise add |
| 437 | const OP_VSUB: i64 = 81 |
| 438 | const OP_VMUL: i64 = 82 |
| 439 | const OP_VDIV: i64 = 83 // signed int / float |
| 440 | const OP_VFADD: i64 = 84 // fp variant (vfadd.vv) |
| 441 | const OP_VFSUB: i64 = 85 |
| 442 | const OP_VFMUL: i64 = 86 |
| 443 | const OP_VFDIV: i64 = 87 |
| 444 | const OP_VLE: i64 = 88 // vector load element (vle32.v / vle64.v) |
| 445 | const OP_VSE: i64 = 89 // vector store element |
| 446 | const OP_VSETVLI: i64 = 90 // explicit vl/vtype setup |
| 447 | const OP_VMV_S_X: i64 = 91 // scalar broadcast into vector |
| 448 | const OP_VREDSUM: i64 = 92 // reduction sum (for softmax denom, norm) |
| 454 | const OP_SIMD_VDOT_I16_X16: i64 = 93 // (a:i16x16) . (b:i16x16) -> i64 scalar |
| 459 | const OP_SIMD_VREDUCE_MIN_I16_X16: i64 = 94 // (v:*i64) -> i64 sign-ext min |
| 460 | const OP_SIMD_VREDUCE_MAX_I16_X16: i64 = 95 // (v:*i64) -> i64 sign-ext max |
| 463 | const OP_SIMD_VSADD_I16_X16: i64 = 96 // (a:*i64, b:*i64, out:*i64) -> void |
| 465 | const OP_SIMD_VSSUB_I16_X16: i64 = 97 |
| 468 | const OP_SIMD_VSADDU_I16_X16: i64 = 98 |
| 469 | const OP_SIMD_VSSUBU_I16_X16: i64 = 99 |
| 472 | const OP_SIMD_VMIN_LANE_I16_X16: i64 = 100 |
| 473 | const OP_SIMD_VMAX_LANE_I16_X16: i64 = 101 |
| 474 | const OP_SIMD_VADD_LANE_I16_X16: i64 = 102 |
| 475 | const OP_SIMD_VSUB_LANE_I16_X16: i64 = 103 |
| 476 | const OP_SIMD_VMUL_LANE_I16_X16: i64 = 104 |
| 482 | const OP_SIMD_VSLL_I16_X16: i64 = 105 |
| 483 | const OP_SIMD_VSRL_I16_X16: i64 = 106 |
| 484 | const OP_SIMD_VSRA_I16_X16: i64 = 107 |
| 490 | const OP_SIMD_VREDUCE_SUM_I16_X16: i64 = 108 |
| 493 | const OP_SIMD_VBROADCAST_I16_X16: i64 = 109 |
| 498 | const OP_SIMD_VADD_I8_X32: i64 = 110 |
| 499 | const OP_SIMD_VSUB_I8_X32: i64 = 111 |
| 500 | const OP_SIMD_VSADD_I8_X32: i64 = 112 // signed saturating |
| 501 | const OP_SIMD_VSSUB_I8_X32: i64 = 113 // signed saturating |
| 505 | const OP_SIMD_VREDUCE_SUM_I8_X32: i64 = 114 |
| 508 | const OP_SIMD_VBROADCAST_I8_X32: i64 = 115 |
| 513 | const OP_SIMD_VADD_I32_X8: i64 = 116 |
| 514 | const OP_SIMD_VSUB_I32_X8: i64 = 117 |
| 515 | const OP_SIMD_VMUL_I32_X8: i64 = 118 |
| 516 | const OP_SIMD_VSADD_I32_X8: i64 = 119 |
| 517 | const OP_SIMD_VSSUB_I32_X8: i64 = 120 |
| 521 | const OP_SIMD_VREDUCE_SUM_I32_X8: i64 = 121 |
| 524 | const OP_SIMD_VBROADCAST_I32_X8: i64 = 122 |
| 526 | const OP_SIMD_VADD_I64_X4: i64 = 123 |
| 527 | const OP_SIMD_VSUB_I64_X4: i64 = 124 |
| 528 | const OP_SIMD_VMUL_I64_X4: i64 = 125 |
| 529 | const OP_SIMD_VSADD_I64_X4: i64 = 126 |
| 530 | const OP_SIMD_VSSUB_I64_X4: i64 = 127 |
| 531 | const OP_SIMD_VREDUCE_SUM_I64_X4: i64 = 128 |
| 532 | const OP_SIMD_VBROADCAST_I64_X4: i64 = 129 |
| 538 | const OP_RDTSC: i64 = 130 |
| 539 | const OP_UMULHI: i64 = 131 // unsigned 64x64 -> high 64 bits (x86 mulq); G2 wide-multiply |
| 540 | const OP_ADC_ACC: i64 = 132 // G3 native add-with-carry: (hi:lo) += into a 3-word *acc (addq;adcq;adcq) |
| 543 | const OP_CPUID_EBX: i64 = 133 // x86 cpuid(leaf=op0, subleaf=op1) -> EBX (feature register). For the |
| 546 | const OP_WFI: i64 = 70 |
| 547 | const OP_CSR_READ: i64 = 71 |
| 548 | const OP_CSR_WRITE: i64 = 72 |
| 549 | const OP_FENCE: i64 = 73 |
| 550 | const OP_MRET: i64 = 74 |
| 554 | const VK_CONST_INT: i64 = 0 |
| 555 | const VK_PARAM: i64 = 1 |
| 556 | const VK_INSTR: i64 = 2 |
| 561 | const VK_GLOBAL: i64 = 3 |
| 564 | const VK_FUNC_ADDR: i64 = 4 |
| 571 | const TY_VOID: i64 = 0 |
| 572 | const TY_BOOL: i64 = 1 |
| 573 | const TY_I8: i64 = 2 |
| 574 | const TY_I16: i64 = 3 |
| 575 | const TY_I32: i64 = 4 |
| 576 | const TY_I64: i64 = 5 |
| 577 | const TY_PTR: i64 = 6 |
| 578 | const TY_STRUCT: i64 = 7 |
| 579 | const TY_PARAM: i64 = 8 // generic type variable (T, E) inside a template |
| 583 | const TY_F32: i64 = 9 // single precision (RV64F) |
| 584 | const TY_F64: i64 = 10 // double precision (RV64D) |
| 589 | const TY_ARRAY: i64 = 11 |
| 593 | const TY_FUNC: i64 = 12 |
| 613 | const TY_SLICE: i64 = 13 |
| 614 | const NX_SLICE_HDR_BYTES: i64 = 16 // {data, len} |
| 615 | const NX_SLICE_LEN_OFFSET: i64 = 8 // byte offset of len within the header |
| 619 | const VL_REGISTER: i64 = 0 |
| 620 | const VL_SPILLED: i64 = 1 |
| 625 | const VL_REMAT: i64 = 2 |
| 633 | const VL_ALLOCA: i64 = 3 |
| 637 | const VAL_CONST: i64 = 0 |
| 638 | const VAL_PARAM: i64 = 1 |
| 639 | const VAL_INSTR: i64 = 2 |
functions
| none |