rv64im_min_sim.nx

rv64im_min_sim.nx -- single-cycle RV64IM-min behavioural simulator. First runnable thing in nishi-silicon. Ties the previously-shipped modules together so RV64IM programs execute end-to-end in pure NishiLang: decoder (rv64im_min_decoder) -> opcode kind + operand fields ALU (rv64im_min_alu) -> arithmetic compute regfile (rv64im_min_regfile) -> 32 GPRs storage CSR (rv64im_min_csr) -> M-mode CSRs CLINT (rv64im_min_clint) -> MTIP interrupt source UART (rv64im_min_uart) -> debug console Why "single-cycle" not "pipelined": a single-cycle model is the canonical "first simulator" -- one instruction per simulator step, no pipeline hazards, no fetch/decode/execute overlap. Verifies the combinational + sequential modules without the complexity of IF/ID/EX latches or hazard detection. Pipelined model lands in a follow-on commit; Tier A FPGA bitstream gets the pipelined version (no point fabbing a single-cycle core when the pipelined one is also single-issue in-order and only marginally larger). What this enables: - Run RV64IM .text segments emitted by the SOVEREIGN toolchain (nx_cc -> nxasm rv64 backend); gcc/llvm are a diff-lane reference ONLY, never on the chain (this sim IS the genesis ISA spec + the sovereign-cycle yardstick) - Validate the decoder + ALU against any RV64IM disassembler - Boot the nishi-os kernel ELF (after the load/store unit + memory bus land in a follow-on commit) before fabbing FPGA bitstream Status: SEED. 2026-05-26. Single-cycle non-interrupt loop. Interrupt handling, load/store, mret/ecall flow land per the TODO markers below.