rv64im_min_gpu.nx

rv64im_min_gpu.nx -- a SOVEREIGN GPU-class command-submission controller device model (the 4th device class for the driver-from-spec arc, toward the GPU/CUDA/DirectX trajectory). Twin of rv64im_min_nvme.nx but for the GPU SUBMISSION model: a command RING in guest RAM, a write-to- submit DOORBELL, a monotonic FENCE/seqno the driver polls for completion, and a RESULTPEEK binding-proof register. It COMPOSES with the sovereign SPIR-V lane: a command packet MUST carry the SPIR-V magic 0x07230203 (a compute-shader dispatch) or the device refuses to execute -- so a GPU driver authored from an op-list spec drives a real SPIR-V-validated dispatch. The device models ONE controller window [0x10007000, 0x10008000) -- free of the virtio (0x10001/ 0x10002), nvme (0x10003-0x10005), nndev (0x10005), and mmu (0x10006) windows (additive). KEY behaviour: on a DOORBELL write the device fetches the command packet from RING_BASE (STRUCT_WALK: opcode + spirv_magic + operand + seqno), validates the SPIR-V magic, "executes" the dispatch, bumps FENCE to the submitted seqno, and latches RESULTPEEK = (operand<<16)|seqno. GPU/Vulkan/SPIR-V here is the last-mile interop PROBE + a measuring stick to EXCEED -- the emitted driver + the op-list shapes are Nishi-native (the device identity lives ENTIRELY in the spec; the canonical op-list emitter nx_drv_proto_emit knows zero GPU). Status: SEED. 2026-06-13. Enable + command-ring doorbell dispatch + SPIR-V-magic-gated fence/result. license_tier: ORIGINAL