rv64im_min_kernel_boot_smoke.nx

rv64im_min_kernel_boot_smoke.nx -- boot the nishi-os kernel ELF in sim. End-to-end test that closes the loop from "shipped NishiHDL modules" -> "sim runs hand-coded RV64IM" -> "ELF loader works" -> "ACTUAL KERNEL BOOTS in our pure-NishiLang substrate, no qemu, no external interpreter" What this proves: The 11 NishiHDL files under nishi-silicon/hdl/ collectively implement enough of RV64IM-min that the shipped nishi-os kernel ELF executes correctly: at minimum, the kernel's selftest path prints the first [m0-mcs-live] UART marker to our captured tx_buf within the step budget. What this DOES NOT prove (still needed for Tier A FPGA bring-up): - nishi-synth gate-netlist emit (HDL graph -> Verilog/gates) - Yosys + nextpnr place-and-route (gates -> ECP5 bitstream) - FPGA board execution (bitstream -> ULX3S -> physical UART) Status: SEED. 2026-05-26. Initial harness. Step budget is generous (10M) since the kernel runs many cycles before reaching the first observable marker.