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nx_rv64_mmu_oracle.nx

buildroot/runtime/_hdl_build/nx_rv64_mmu_oracle.nx

9067 B111 linesdepth 5pulls 18 transitivereach 0 importersview sourcekind tooltopic rv64
docsdependenciesstructsconstsfunctions

about

nx_rv64_mmu_oracle.nx -- ROADMAP R2 (privilege, part 3): validate the golden sim's Sv39 MMU TRANSLATION -- the OS's virtual-memory foundation -- against QEMU. The sim's nx_sv39_walk supports gigapage/megapage/4K leaves; this uses GIGAPAGE (level-2 leaf) mappings for a simple 1-table setup. M-mode builds a root page table with 3 gigapage PTEs: [0] identity VA 0x00000000-0x3FFFFFFF -> PA identity (covers UART 0x10000000 + finisher 0x100000) [1] REMAP VA 0x40000000-0x7FFFFFFF -> PA 0x80000000-0xBFFFFFFF (the translation under test) [2] identity VA 0x80000000-0xBFFFFFFF -> PA identity (code + RAM) sets satp (Sv39, root@0x80005000), PMP allow-all, drops to S-mode with paging ON. S-mode stores 0xC3 through the REMAPPED VA 0x40003000 (-> PA 0x80003000), reads it back through the IDENTITY VA 0x80003000 (-> PA 0x80003000) -- if the walk translates both correctly they alias the same physical byte -> 0xC3. expect UART = c3 2a. expect_exit: 0 NEVER-BRICK: simulation, writes 0 hardware state.

dependencies 13 imports · 0 importers

nx_syscalls.nx nx_itoa_lib.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_virtio.nx nx_rv64_mmu_oracle.nx

diagram shows first 10 each side; +3 more imports, +0 more importers in the complete lists below.

imports: nx_syscalls.nxnx_itoa_lib.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_virtio.nxrv64im_min_mmu.nxrv64im_min_sim.nxnx_rv64_asm.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts sys_write sys_mmap ra_put ra_u ra_i ra_s ra_r ra_j g_pn nxi_out nxi_fd sys_mmap ↻ ccz_cat_num sys_write ↻ sys_munmap nx_rv64im_rf_init nx_rv64im_csr_init nx_clint_init nx_uart_init nx_rv64im_sim_init nx_rv64im_sim_run nx_rv64im_sim_step nx_clint_tick nx_clint_update_mtip nx_rv64im_csr_tick_mcycle nx_clint_mtip_get nx_rv64im_csr_read nx_csr_addr_to_slot nx_rv64im_sim_take_trap nx_rv64im_csr_read ↻ nx_rv64im_csr_write nx_csr_addr_to_slot ↻ nx_csr_is_read_only nx_rv64im_xlate nx_rv64im_csr_read ↻ nx_rv64im_is_device sys_mmap ↻ nx_sv39_walk

structs

none

consts

24const DMEM_MAGIC_4096: i64 = 4096
25const DMEM_MAGIC_10000000: i64 = 10000000
36const DMEM_BASE: i64 = 0x80000000
37const DMEM_SIZE: i64 = 65536
38const CSR_PMPCFG0: i64 = 0x3A0
39const CSR_PMPADDR0: i64 = 0x3B0
40const CSR_SATP: i64 = 0x180
41const CSR_MSTATUS: i64 = 0x300
42const CSR_MEPC: i64 = 0x341

functions

27func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: ckmain calls 1: sys_write
32func g_pn(v: i64) -> i64 { nxi_out(v); return 0 }
called by 1: main calls 1: nxi_out
33func g_hx(v: i64) -> i64 { let b: *u8=sys_mmap(4); let n0: i64=(v>>4)&15; let n1: i64=v&15; if n0<10 { b[0]=(48+n0) as u8 } else { b[0]=(87+n0) as u8 } if n1<10 { b[1]=(48+n1) as u8 } else { b[1]=(87+n1) as u8 } b[2]=32 as u8; sys_write(1,b,3); return 0 }
called by 1: main calls 2: sys_mmapsys_write
34func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c }
called by 1: main calls 1: g_puts
44func main() -> i64
calls 22: g_putssys_mmapra_putra_ura_ira_s+16