code wiki / _hdl_build / rv64im_min_hot_report.nx

rv64im_min_hot_report.nx

buildroot/runtime/_hdl_build/rv64im_min_hot_report.nx

12981 B302 linesdepth 7pulls 18 transitivereach 1 importersview sourcekind librarytopic rv64im
docsdependenciesstructsconstsfunctions

about

rv64im_min_hot_report.nx -- silicon-feedback loop closure. Takes a sim that has run with per-PC cycle attribution on + the kernel ELF byte buffer; produces: 1. Top-N hot functions by cycle count (function name + cycles + % of total) 2. A silicon-acceleration candidate list -- one entry per hot function with a proposed silicon instruction add + an estimated ROI score (cycle savings / silicon gate cost) Compositional: stitches together rv64im_min_sim (per-PC cycle attribution, commit 4365e77) + rv64im_min_elf_loader (loaded the kernel into sim mem) + rv64im_min_symtab (parsed FUNC symbols from .symtab) This is the FIRST measurement-driven silicon-design-decision tool in the Nishi stack. Per [[feedback-honest-perf-verdict]]: silicon instruction additions need cycle evidence per function, not guesses. This is the producer. Per ZERO_TO_ADVANCED.md M3: "first silicon-feedback-informed spec edit" is the next milestone that uses this report's output to modify rv64im_min_target_spec.md with one or more new MUST/SHOULD instructions. Status: SEED. 2026-05-26. Reports + candidate-list shape; the silicon-cost estimator + per-instruction ROI scoring are hand-curated today; future commits learn the cost model from nishi-synth gate-count data.

dependencies 11 imports · 1 importers

nx_syscalls.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_sim.nx rv64im_min_elf_loader.nx rv64im_min_hot_report.nx rv64im_min_multi_tier_roi.nx

diagram shows first 10 each side; +1 more imports, +0 more importers in the complete lists below.

imports: nx_syscalls.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_sim.nxrv64im_min_elf_loader.nxrv64im_min_symtab.nx

imported by: rv64im_min_multi_tier_roi.nx

structs

49struct NxFuncCycles
141struct NxSiliconCandidate

consts

153const NX_SILICON_PROP_NONE: i64 = 0
154const NX_SILICON_PROP_POPCOUNT: i64 = 1 // Zbb cpop equivalent
155const NX_SILICON_PROP_CTZ_CLZ: i64 = 2 // Zbb ctz/clz
156const NX_SILICON_PROP_ROTATE: i64 = 3 // Zbb rori/rol
157const NX_SILICON_PROP_SIMD_I32x4: i64 = 4 // 4-lane i32 SIMD (V-ext lite)
158const NX_SILICON_PROP_MAC_FUSED: i64 = 5 // multiply-add-accumulate one cycle
159const NX_SILICON_PROP_BARREL_SHIFT: i64 = 6 // single-cycle 64-bit shift any amount
160const NX_SILICON_PROP_BRANCH_PREDICT: i64 = 7 // 2-level BHT
161const NX_SILICON_PROP_LOAD_FAST: i64 = 8 // sub-cycle MMIO read for uart_print poll
162const NX_SILICON_PROP_DIVIDER_FAST: i64 = 9 // Radix-4 SRT divider
163const NX_SILICON_PROP_N: i64 = 10

functions

55func nx_hot_aggregate_by_function(sim: *NxRv64imSim, symtab: *NxSymtab,
102func nx_hot_topn(funcs: *NxFuncCycles, n_funcs: i64, n_top: i64) -> i64
167func nx_silicon_speedup_for(kind: i64) -> i64
182func nx_silicon_gates_for(kind: i64) -> i64
199func nx_silicon_candidate_propose(name_ptr: *u8, name_len: i64) -> i64
215func nx_substr_match(hay: *u8, hay_len: i64, needle: *u8, needle_len: i64) -> i64
234func nx_silicon_build_candidates(hot: *NxFuncCycles, n_hot: i64,
276func nx_hot_print_report(hot: *NxFuncCycles, n_hot: i64,