code wiki / _hdl_build / nx_rv64_realc_gate.nx

nx_rv64_realc_gate.nx

buildroot/runtime/_hdl_build/nx_rv64_realc_gate.nx

7356 B82 linesdepth 7pulls 19 transitivereach 0 importersview sourcekind gate/prooftopic rv64
docsdependenciesstructsconstsfunctions

about

nx_rv64_realc_gate.nx -- MILESTONE: the sovereign emulator runs REAL gcc-compiled C code, bit-identical to QEMU. Loads knowledge/hw/realc.bin -- a bare-metal C program (recursion/fib + bubble sort + accumulation) compiled by riscv64-linux-gnu-gcc -march=rv64im (real register allocation, stack frames, function calls; no hand-assembly) -- runs it on the GOLDEN SIM (UART captured) and confirms UART == 01 09 37 27 2a (which == qemu-system-riscv64, proven separately). Also runs it on the fast interp + tiered/JIT engines to confirm they EXECUTE real compiler output to completion (halt via the finisher, not maxsteps). Proves the emulator isn't just passing hand-crafted tests -- it runs genuine compiler output. expect_exit: 0 NEVER-BRICK: simulation, writes 0 hardware state.

dependencies 14 imports · 0 importers

nx_syscalls.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_virtio.nx rv64im_min_mmu.nx nx_rv64_realc_gate.nx

diagram shows first 10 each side; +4 more imports, +0 more importers in the complete lists below.

imports: nx_syscalls.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_virtio.nxrv64im_min_mmu.nxrv64im_min_sim.nxnx_rv64_fast.nxnx_rv64_jit.nxnx_rv64_tier.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts sys_write sys_mmap sys_read_file sys_openat_rd sys_lseek sys_mmap ↻ sys_read sys_close sys_exit g_pn sys_mmap ↻ sys_write ↻ nx_rv64im_rf_init nx_rv64im_csr_init nx_clint_init nx_uart_init nx_rv64im_sim_init nx_rv64im_sim_run nx_rv64im_sim_step nx_clint_tick nx_clint_update_mtip nx_rv64im_csr_tick_mcycle nx_clint_mtip_get nx_rv64im_csr_read nx_csr_addr_to_slot nx_rv64im_sim_take_trap nx_rv64im_csr_read ↻ nx_rv64im_csr_write nx_csr_addr_to_slot ↻ nx_csr_is_read_only nx_rv64im_xlate nx_rv64im_csr_read ↻ nx_rv64im_is_device sys_mmap ↻ nx_sv39_walk nx_mmu_inrange nx_mmu_rd64 nx_mmu_inrange ↻

structs

none

consts

28const DMEM_BASE: i64 = 0x80000000
29const DMEM_SIZE: i64 = 65536

functions

23func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: ckmain calls 1: sys_write
24func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 }
called by 1: main calls 2: sys_mmapsys_write
25func g_hx(v: i64) -> i64 { let b: *u8=sys_mmap(4); let n0: i64=(v>>4)&15; let n1: i64=v&15; if n0<10 { b[0]=(48+n0) as u8 } else { b[0]=(87+n0) as u8 } if n1<10 { b[1]=(48+n1) as u8 } else { b[1]=(87+n1) as u8 } b[2]=32 as u8; sys_write(1,b,3); return 0 }
called by 1: main calls 2: sys_mmapsys_write
26func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c }
called by 1: main calls 1: g_puts
31func main() -> i64
calls 22: g_putssys_mmapsys_read_filesys_exitg_pnnx_rv64im_rf_init+16