nx_rv64_realc_gate.nx source

1// nx_rv64_realc_gate.nx -- MILESTONE: the sovereign emulator runs REAL gcc-compiled C code, bit-identical to QEMU. 2// Loads knowledge/hw/realc.bin -- a bare-metal C program (recursion/fib + bubble sort + accumulation) compiled by 3// riscv64-linux-gnu-gcc -march=rv64im (real register allocation, stack frames, function calls; no hand-assembly) -- 4// runs it on the GOLDEN SIM (UART captured) and confirms UART == 01 09 37 27 2a (which == qemu-system-riscv64, proven 5// separately). Also runs it on the fast interp + tiered/JIT engines to confirm they EXECUTE real compiler output to 6// completion (halt via the finisher, not maxsteps). Proves the emulator isn't just passing hand-crafted tests -- it 7// runs genuine compiler output. expect_exit: 0 NEVER-BRICK: simulation, writes 0 hardware state. 8import "nx_syscalls.nx" 9import "nishi_hdl_primitives.nx" 10import "rv64im_min_decoder.nx" 11import "rv64im_min_alu.nx" 12import "rv64im_min_regfile.nx" 13import "rv64im_min_csr.nx" 14import "rv64im_min_clint.nx" 15import "rv64im_min_uart.nx" 16import "rv64im_min_virtio.nx" 17import "rv64im_min_mmu.nx" 18import "rv64im_min_sim.nx" 19import "nx_rv64_fast.nx" 20import "nx_rv64_jit.nx" 21import "nx_rv64_tier.nx" 22 23func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 24func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 } 25func g_hx(v: i64) -> i64 { let b: *u8=sys_mmap(4); let n0: i64=(v>>4)&15; let n1: i64=v&15; if n0<10 { b[0]=(48+n0) as u8 } else { b[0]=(87+n0) as u8 } if n1<10 { b[1]=(48+n1) as u8 } else { b[1]=(87+n1) as u8 } b[2]=32 as u8; sys_write(1,b,3); return 0 } 26func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c } 27 28const DMEM_BASE: i64 = 0x80000000 29const DMEM_SIZE: i64 = 65536 30 31func main() -> i64 { 32 g_puts("nx_rv64_realc_gate (the sovereign emulator runs REAL gcc -march=rv64im compiled C -- vs QEMU 01 09 37 27 2a)\n" as *u8) 33 var pass: i64=0; var total: i64=0 34 let lenbox: *i64=sys_mmap(16) as *i64 35 let code: *u8=sys_read_file("knowledge/hw/realc.bin" as *u8, lenbox) 36 if (code as i64)==0 { g_puts(" NO realc.bin -- compile realprog.c first\n" as *u8); sys_exit(1); return 1 } 37 let nb: i64=lenbox[0] 38 g_puts(" loaded realc.bin: "); g_pn(nb); g_puts(" bytes of gcc-compiled RV64IM\n" as *u8) 39 40 // --- GOLDEN SIM (UART-modeled): the correctness reference --- 41 let rf_storage: *i64=sys_mmap(8*NX_RV64IM_RF_N_REGS) as *i64; let csr_storage: *i64=sys_mmap(8*NX_CSR_SLOT_N) as *i64 42 let clint_storage: *i64=sys_mmap(8*NX_CLINT_SLOT_N) as *i64; let uart_storage: *i64=sys_mmap(8*NX_UART_SLOT_N) as *i64 43 let mem: *u8=sys_mmap(DMEM_SIZE); let tx_buf: *u8=sys_mmap(256) 44 let rf: *NxRv64imRegfile=sys_mmap(64) as *NxRv64imRegfile; let csr: *NxRv64imCsrFile=sys_mmap(64) as *NxRv64imCsrFile 45 let clint: *NxClint=sys_mmap(64) as *NxClint; let uart: *NxUart=sys_mmap(64) as *NxUart; let sim: *NxRv64imSim=sys_mmap(128) as *NxRv64imSim 46 nx_rv64im_rf_init(rf, rf_storage); nx_rv64im_csr_init(csr, csr_storage, 0); nx_clint_init(clint, clint_storage); nx_uart_init(uart, uart_storage, tx_buf, 256) 47 nx_rv64im_sim_init(sim, rf, csr, clint, uart, DMEM_BASE, mem, DMEM_SIZE, 0) 48 var i: i64=0; while i<nb { mem[i]=code[i]; i=i+1 } 49 nx_rv64im_sim_run(sim, 200000000) 50 let n: i64=nx_uart_tx_count(uart) 51 g_puts(" golden sim UART ("); g_pn(n); g_puts(" bytes): "); i=0; while i<n { g_hx(tx_buf[i] as i64); i=i+1 } g_puts("\n" as *u8) 52 var t1: i64=0 53 if n==5 { if tx_buf[0]==(0x01 as u8) { if tx_buf[1]==(0x09 as u8) { if tx_buf[2]==(0x37 as u8) { if tx_buf[3]==(0x27 as u8) { if tx_buf[4]==(0x2a as u8) { t1=1 } } } } } } 54 pass=pass+ck("T1: golden sim runs the gcc-compiled C (sort+fib+sum) -> UART = 01 09 37 27 2a (== QEMU)" as *u8, t1); total=total+1 55 56 // --- FAST interp + TIERED: confirm they EXECUTE real compiler output to completion (halt via finisher, not maxsteps) --- 57 let opk: *i64=sys_mmap(1024*8) as *i64; let rd: *i64=sys_mmap(1024*8) as *i64; let rs1: *i64=sys_mmap(1024*8) as *i64; let rs2: *i64=sys_mmap(1024*8) as *i64; let imm: *i64=sys_mmap(1024*8) as *i64 58 let nc: i64=fk_predecode(code, nb, opk, rd, rs1, rs2, imm) 59 let freg: *i64=sys_mmap(32*8) as *i64; let fmem: *u8=sys_mmap(DMEM_SIZE); var z: i64=0; while z<32 { freg[z]=0; z=z+1 } var m: i64=0; while m<nb { fmem[m]=code[m]; m=m+1 } 60 let ftx: *u8=sys_mmap(64); fk_tx_reset(ftx) 61 let fsteps: i64=fk_run(opk, rd, rs1, rs2, imm, nc, freg, fmem, DMEM_SIZE, 200000000, (0 as i64) as *NxVirtioMmio) 62 let fn: i64=fk_tx_count() 63 var t2: i64=0; if fn==5 { if ftx[0]==(0x01 as u8) { if ftx[1]==(0x09 as u8) { if ftx[2]==(0x37 as u8) { if ftx[3]==(0x27 as u8) { if ftx[4]==(0x2a as u8) { t2=1 } } } } } } 64 g_puts(" fast interp: executed "); g_pn(fsteps); g_puts(" instr, UART="); var fi: i64=0; while fi<fn { let bb: i64=ftx[fi] as i64; let hb: *u8=sys_mmap(4); let h0: i64=(bb>>4)&15; let h1: i64=bb&15; if h0<10 {hb[0]=(48+h0) as u8} else {hb[0]=(87+h0) as u8} if h1<10 {hb[1]=(48+h1) as u8} else {hb[1]=(87+h1) as u8} hb[2]=32 as u8; sys_write(1,hb,3); fi=fi+1 } g_puts("\n" as *u8) 65 pass=pass+ck("T2: the fast interpreter runs the gcc-compiled code -> UART == 01 09 37 27 2a (== QEMU; real calls/stack/loops)" as *u8, t2); total=total+1 66 let treg: *i64=sys_mmap(32*8) as *i64; let tmem: *u8=sys_mmap(DMEM_SIZE); let stats: *i64=sys_mmap(64) as *i64; z=0; while z<32 { treg[z]=0; z=z+1 } m=0; while m<nb { tmem[m]=code[m]; m=m+1 } 67 let ttx: *u8=sys_mmap(64); fk_tx_reset(ttx) 68 let tsteps: i64=tier_run(opk, rd, rs1, rs2, imm, nc, treg, tmem, DMEM_SIZE, 200000000, (0 as i64) as *NxVirtioMmio, 2, stats) 69 let tn: i64=fk_tx_count() 70 var t3: i64=0; if tn==5 { if ttx[0]==(0x01 as u8) { if ttx[1]==(0x09 as u8) { if ttx[2]==(0x37 as u8) { if ttx[3]==(0x27 as u8) { if ttx[4]==(0x2a as u8) { t3=1 } } } } } } 71 g_puts(" tiered/JIT: executed "); g_pn(tsteps); g_puts(" instr, "); g_pn(stats[1]); g_puts(" loops JIT-compiled (real int loops now JIT via *W), UART matches="); g_pn(t3); g_puts("\n" as *u8) 72 pass=pass+ck("T3: the tiered/JIT engine runs the gcc-compiled code -> UART == 01 09 37 27 2a (JITs real int loops, CORRECT)" as *u8, t3); total=total+1 73 74 var okall: i64=0; if pass==total { okall=1 } 75 g_puts("---- nx_rv64_realc_gate: passed "); g_pn(pass); g_puts(" / "); g_pn(total); g_puts(" ----\n" as *u8) 76 if okall==1 { 77 let logf: i64=sys_openat_append("knowledge/status/realc.log" as *u8, 420) 78 if logf>=0 { let z2: i64=sys_write(logf,"NXRV64REALC GREEN: the sovereign emulator runs REAL gcc -march=rv64im compiled C (recursion/sort/sum) -- golden sim UART 01 09 37 27 2a == QEMU; fast+tiered execute real compiler output to completion. not just hand-crafted tests -- genuine compiler output.\n" as *u8,290); sys_close(logf) } 79 g_puts("verdict=GREEN (the sovereign emulator runs REAL gcc-compiled C bit-identical to QEMU -- genuine compiler output, not hand-assembly; the 'runs real software' milestone)\n" as *u8); sys_exit(0); return 0 80 } 81 g_puts("verdict=RED\n" as *u8); sys_exit(1); return 1 82}