rv64im_min_nvme.nx

rv64im_min_nvme.nx -- a SOVEREIGN NVMe-class PCI/MMIO controller device model (X-DRV-W1 stage B, the 2nd device class). This is the TWIN of rv64im_min_virtio.nx but for a genuinely DIFFERENT bring-up protocol: where virtio is a straight-line OR-write status ladder, NVMe is a write-then-POLL enable handshake (CC.EN -> poll CSTS.RDY) plus an admin Submission/Completion queue pair bound by 64-bit BASE-ADDRESS registers (ASQ/ACQ, NOT a single PFN<<12), a 64-byte SQE the driver lays in guest RAM, ring advance by TAIL/HEAD DOORBELL writes, and a 16-byte CQE with a PHASE-TAG bit the driver polls. The device models ONE controller window [0x10003000, 0x10003000+0x2000). The KEY behaviour: on a SQ-Tail-doorbell write (off_sq0tdbl) the device runs the doorbell DMA -- it fetches the 64-byte SQE from ASQ_base (STRUCT_WALK over guest RAM: reads opcode + CID), executes a trivial admin command, POSTS a 16-byte CQE into ACQ_base (writes SQHD/CID/status with the phase bit set), and latches a NvmeCqPeek RO word = (CID<<16)|status|phase. CSTS.RDY is a latched flop set when CC.EN was written 1 (cleared on CC.EN=0 reset), so the driver's poll-until-RDY loop terminates. The virtio + net device models are untouched (additive, separate instance) so PROOF-1's SECTGATE stays GREEN. NVMe/PCI here is a last-mile interop PROBE + a measuring stick to EXCEED -- the emitted driver and the shapes are Nishi-native (the device identity lives ENTIRELY in the spec; the shape library that emits the driver knows zero NVMe). Status: SEED. 2026-06-13. Enable handshake + admin SQ/CQ doorbell DMA + phase-tagged CQE. license_tier: ORIGINAL