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nx_rv64_sdeleg_oracle.nx

buildroot/runtime/_hdl_build/nx_rv64_sdeleg_oracle.nx

9344 B117 linesdepth 5pulls 18 transitivereach 0 importersview sourcekind tooltopic rv64
docsdependenciesstructsconstsfunctions

about

nx_rv64_sdeleg_oracle.nx -- ROADMAP R2 (privilege, part 2): validate the golden sim's S-MODE TRAP DELEGATION -- the REAL kernel trap path -- against QEMU. M-mode sets up PMP allow-all (harmless no-op in the sim; lets S-mode touch memory in QEMU), delegates ecall-from-S (medeleg bit 9) to S-mode, sets MPP=S DETERMINISTICALLY (clear-then-set: the sim resets MPP=M but QEMU resets MPP=U), mret's DOWN to S-mode. In S-mode an ecall (cause 9) is DELEGATED to stvec (the S-handler), which reads scause(=9), bumps sepc, sret's back. Then S-mode emits scause + sentinel + halts. If sim==QEMU, the delegation path (medeleg/stvec/scause/sepc/sstatus.SPP/sret) is validated vs the world reference. expect UART = 09 2a. expect_exit: 0 NEVER-BRICK: simulation, writes 0 hardware state.

dependencies 12 imports · 0 importers

nx_syscalls.nx nx_itoa_lib.nx nishi_hdl_primitives.nx rv64im_min_decoder.nx rv64im_min_alu.nx rv64im_min_regfile.nx rv64im_min_csr.nx rv64im_min_clint.nx rv64im_min_uart.nx rv64im_min_virtio.nx nx_rv64_sdeleg_oracle.nx

diagram shows first 10 each side; +2 more imports, +0 more importers in the complete lists below.

imports: nx_syscalls.nxnx_itoa_lib.nxnishi_hdl_primitives.nxrv64im_min_decoder.nxrv64im_min_alu.nxrv64im_min_regfile.nxrv64im_min_csr.nxrv64im_min_clint.nxrv64im_min_uart.nxrv64im_min_virtio.nxrv64im_min_sim.nxnx_rv64_asm.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts sys_write sys_mmap ra_put ra_u ra_i ra_s ra_j g_pn nxi_out nxi_fd sys_mmap ↻ ccz_cat_num sys_write ↻ sys_munmap nx_rv64im_rf_init nx_rv64im_csr_init nx_clint_init nx_uart_init nx_rv64im_sim_init nx_rv64im_sim_run nx_rv64im_sim_step nx_clint_tick nx_clint_update_mtip nx_rv64im_csr_tick_mcycle nx_clint_mtip_get nx_rv64im_csr_read nx_csr_addr_to_slot nx_rv64im_sim_take_trap nx_rv64im_csr_read ↻ nx_rv64im_csr_write nx_csr_addr_to_slot ↻ nx_csr_is_read_only nx_rv64im_xlate nx_rv64im_csr_read ↻ nx_rv64im_is_device sys_mmap ↻ nx_sv39_walk nx_mmu_inrange

structs

none

consts

20const DMEM_MAGIC_4096: i64 = 4096
21const DMEM_MAGIC_10000000: i64 = 10000000
32const DMEM_BASE: i64 = 0x80000000
33const DMEM_SIZE: i64 = 65536
34const CSR_PMPCFG0: i64 = 0x3A0
35const CSR_PMPADDR0: i64 = 0x3B0
36const CSR_MEDELEG: i64 = 0x302 // machine EXCEPTION delegation (0x303 is mideleg = INTERRUPT delegation -- ecall is an exception!)
37const CSR_MSTATUS: i64 = 0x300
38const CSR_MEPC: i64 = 0x341
39const CSR_STVEC: i64 = 0x105
40const CSR_SEPC: i64 = 0x141
41const CSR_SCAUSE: i64 = 0x142

functions

23func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: ckmain calls 1: sys_write
28func g_pn(v: i64) -> i64 { nxi_out(v); return 0 }
called by 1: main calls 1: nxi_out
29func g_hx(v: i64) -> i64 { let b: *u8=sys_mmap(4); let n0: i64=(v>>4)&15; let n1: i64=v&15; if n0<10 { b[0]=(48+n0) as u8 } else { b[0]=(87+n0) as u8 } if n1<10 { b[1]=(48+n1) as u8 } else { b[1]=(87+n1) as u8 } b[2]=32 as u8; sys_write(1,b,3); return 0 }
called by 1: main calls 2: sys_mmapsys_write
30func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c }
called by 1: main calls 1: g_puts
43func main() -> i64
calls 21: g_putssys_mmapra_putra_ura_ira_s+15