code wiki / _hdl_build / nx_cell_sink.nx
nx_cell_sink.nx
buildroot/runtime/_hdl_build/nx_cell_sink.nx
about
nx_cell_sink.nx -- ONE cell-emit interface, TWO backends. The true SIL-3/SIL-1
"one source" closure: a netlist builder written against NxCellSink emits the
SAME gate graph to either
(a) an in-memory NxGsim -> the functional Verifier (nx_gsim_run) runs it,
(b) a .nxgate text sink -> the shipping synth output downstream PnR reads.
So the divider/ALU is described ONCE and the verifier provably checks exactly
what the emitter ships -- no hand-kept copy, no op->kind-only shortcut.
Net allocation: MEM mode hands out integer net ids (g.n_nets++); TEXT mode
allocates a real module wire (nx_hdl_wire, width-typed) and emits the cell
line. Width is used only by TEXT (the sim is word-level / width-agnostic).
dependencies 4 imports · 5 importers
imports: nx_syscalls.nxnx_nxgate_sim.nxnishi_synth_gates.nxnishi_hdl_primitives.nx
imported by: nx_alu_divider.nxnx_alu_select.nxnx_decoder_select.nxnx_mul_wide.nxnx_rtype_control.nx
structs
| 21 | struct NxCellSink |
consts
| 18 | const NX_SINK_MEM: i64 = 0 |
| 19 | const NX_SINK_TEXT: i64 = 1 |
functions
| 29 | func nx_sink_init_mem(k: *NxCellSink, g: *NxGsim) -> i64 |
| 36 | func nx_sink_init_text(k: *NxCellSink, s: *NxSynthSink, m: *NxHdlModule, seq0: i64) -> i64 called by 1: nx_emit_alu_gates |
| 45 | func nx_sink_const(k: *NxCellSink, width: i64, value: i64) -> i64 |
| 67 | func nx_sink_cell(k: *NxCellSink, kind: i64, width: i64, |