code wiki / _hdl_build / nx_mul_wide.nx

nx_mul_wide.nx

buildroot/runtime/_hdl_build/nx_mul_wide.nx

4583 B71 linesdepth 8pulls 8 transitivereach 21 importersview sourcekind librarytopic mul
docsdependenciesstructsconstsfunctions

about

nx_mul_wide.nx -- 64x64 -> 128 unsigned MULTIPLIER as a gate-network (fixes the mulh SIL-1 stub; the high-cascade core fundamental that feeds the divider frontier + all crypto + the future LLM -- nx_dimret => INVEST). The sim's MUL cell gives only the LOW 64 bits (it wraps). The full 128-bit product is assembled from 32-bit limbs (each 32x32 partial product < 2^64, so it fits the i64 cell exactly), schoolbook with column carries: a = ah:al, b = bh:bl (32-bit halves; the &MASK32 also undoes arithmetic >>) ll=al*bl lh=al*bh hl=ah*bl hh=ah*bh c0 = ll_lo c1 = ll_hi + lh_lo + hl_lo (carry1 = c1>>32) c2 = carry1 + lh_hi + hl_hi + hh_lo (carry2 = c2>>32) c3 = carry2 + hh_hi lo = c0 | (c1<<32) ; hi = (c2&MASK32) | ((c3&MASK32)<<32) Output: returns the LO net; writes the HI net to hi_out[0]. Reuses nx_alu_divider's div_const/div_op2 cell-builders (DRY). license_tier: ORIGINAL

dependencies 2 imports · 8 importers

nx_alu_divider.nx nx_cell_sink.nx nx_mul_wide.nx nx_alu_netlist_build_div.nx nx_alu_select.nx nx_latency_metric_test.nx nx_mul_wide_test.nx nx_newton_struct.nx nx_recip64.nx nx_recip_div_w.nx nx_recip_synth.nx

imports: nx_alu_divider.nxnx_cell_sink.nx

imported by: nx_alu_netlist_build_div.nxnx_alu_select.nxnx_latency_metric_test.nxnx_mul_wide_test.nxnx_newton_struct.nxnx_recip64.nxnx_recip_div_w.nxnx_recip_synth.nx

structs

none

consts

21const MW_MASK32: i64 = 4294967295 // 2^32 - 1

functions

26func nx_mul_wide_sink(k: *NxCellSink, na: i64, nb: i64, hi_out: *i64) -> i64
67func nx_mul_wide_synth(g: *NxGsim, na: i64, nb: i64, hi_out: *i64) -> i64