code wiki / _hdl_build / nx_mul_wide.nx
nx_mul_wide.nx
buildroot/runtime/_hdl_build/nx_mul_wide.nx
about
nx_mul_wide.nx -- 64x64 -> 128 unsigned MULTIPLIER as a gate-network (fixes the
mulh SIL-1 stub; the high-cascade core fundamental that feeds the divider
frontier + all crypto + the future LLM -- nx_dimret => INVEST).
The sim's MUL cell gives only the LOW 64 bits (it wraps). The full 128-bit
product is assembled from 32-bit limbs (each 32x32 partial product < 2^64, so
it fits the i64 cell exactly), schoolbook with column carries:
a = ah:al, b = bh:bl (32-bit halves; the &MASK32 also undoes arithmetic >>)
ll=al*bl lh=al*bh hl=ah*bl hh=ah*bh
c0 = ll_lo
c1 = ll_hi + lh_lo + hl_lo (carry1 = c1>>32)
c2 = carry1 + lh_hi + hl_hi + hh_lo (carry2 = c2>>32)
c3 = carry2 + hh_hi
lo = c0 | (c1<<32) ; hi = (c2&MASK32) | ((c3&MASK32)<<32)
Output: returns the LO net; writes the HI net to hi_out[0]. Reuses
nx_alu_divider's div_const/div_op2 cell-builders (DRY). license_tier: ORIGINAL
dependencies 2 imports · 8 importers
imports: nx_alu_divider.nxnx_cell_sink.nx
imported by: nx_alu_netlist_build_div.nxnx_alu_select.nxnx_latency_metric_test.nxnx_mul_wide_test.nxnx_newton_struct.nxnx_recip64.nxnx_recip_div_w.nxnx_recip_synth.nx
structs
| none |
consts
| 21 | const MW_MASK32: i64 = 4294967295 // 2^32 - 1 |
functions
| 26 | func nx_mul_wide_sink(k: *NxCellSink, na: i64, nb: i64, hi_out: *i64) -> i64 |
| 67 | func nx_mul_wide_synth(g: *NxGsim, na: i64, nb: i64, hi_out: *i64) -> i64 called by 5: nxnl_mulhmainnx_newton_mulprodr64_mulhunx_recip_div_w_synth calls 2: nx_sink_init_memnx_mul_wide_sink |