code wiki / _hdl_build / nx_alu_select.nx
nx_alu_select.nx
buildroot/runtime/_hdl_build/nx_alu_select.nx
about
nx_alu_select.nx -- THE one ALU op-select builder, written against NxCellSink.
Called with a MEM sink it fills an NxGsim the Verifier runs; called with a
TEXT sink it emits the .nxgate the shipping synth ships. Same code -> the
verifier proves exactly what the emitter ships (one source, two sinks).
Topology (per op K in 1..N-1): CONST(K) opcode + subnet + EQ(op_in==K) match;
then a cascade MUX(match_K, subnet_K, prev). use_divider=1 makes DIV/DIVU take
the PROVEN restoring divider's quotient and REM/REMU its remainder (the first
hardware invention, in the shipped ALU); use_divider=0 keeps the single-cell
stub from the single-source op->kind map (the baseline that catches holes).
na/nb/nop are pre-existing net ids for a / b / op_in in the sink's net space.
Returns the cascade result net id (caller wires it to the result port / records
it as the sim output).
dependencies 5 imports · 3 importers
imports: nx_cell_sink.nxnx_alu_divider.nxnx_alu_op_kind.nxrv64im_min_alu.nxnx_mul_wide.nx
imported by: nx_alu_select_mem_test.nxnx_cpu_rtype_exec_test.nxsynth_emit_alu_gates.nx
structs
| none |
consts
| 22 | const K_MAGIC_4294967295: i64 = 4294967295 |
| 23 | const K_MAGIC_4294967296: i64 = 4294967296 |
functions
| 27 | func nx_alu_mulh_sink(k: *NxCellSink, na: i64, nb: i64, do_a: i64, do_b: i64) -> i64 |
| 47 | func nx_sext32_sink(k: *NxCellSink, v: i64) -> i64 |
| 61 | func nx_wdiv_u_sink(k: *NxCellSink, na: i64, nb: i64, want_rem: i64) -> i64 |
| 82 | func nx_wdiv_s_sink(k: *NxCellSink, na: i64, nb: i64, want_rem: i64) -> i64 |
| 110 | func nx_alu_build_select(k: *NxCellSink, na: i64, nb: i64, nop: i64, use_divider: i64) -> i64 |