synth_emit_alu_gates.nx

synth_emit_alu_gates.nx -- per-module ALU emitter for .nxgate. First per-RTL-module emitter in the SOVEREIGN canonical chain. Pairs with synth_emit_alu.nx (Wheeler-only Verilog emit, commit d43fbb4) but emits the .nxgate format from nishi_synth_gates.nx (commit 04bca84) instead. Verilog version stays as a test comparator; THIS is the path that ships. Strategy: 29-way cascade MUX over per-op sub-networks. For each op kind K in NX_RV64IM_ALU_*: sub_K = result of K's compute (one cell each for ADD/SUB/...) match_K = (op_in == K_constant) Cascade MUX (associative): intermediate_0 = sub_INVALID (= 64'b0) intermediate_K = mux(match_K, sub_K, intermediate_K-1) result = intermediate_LAST Cell count: ~29 sub-networks + ~29 match constants + ~29 EQ cells + ~29 MUX cells + small overhead = ~150 cells. Trivial for nishi-synth to place on ECP5 BRAM-rich fabric (each ECP5 slice has 4 LUT4 + 4 DFF; 150 cells fits in <50 slices). Status: SEED. 2026-05-26. Covers all 29 NX_RV64IM_ALU_* ops. Multiply-high (mulh/mulhsu/mulhu) emits the cell but downstream synth needs to implement the 64x64->128 multiplier (TODO_SILICON in rv64im_min_alu.nx already noted).