nx_alu_divider.nx

nx_alu_divider.nx -- SYNTHESIZE a correct divider as a gate-network (the invention engine's FIRST real hardware invention; closes the SIL-1 stub where the ALU emitter emitted an ADD cell for DIV). There is no DIV cell kind by design -- division must be BUILT from primitives. This synthesizes a restoring divider (MSB-first, `width` stages) into an NxGsim netlist using only SHL/SHR/SUB/LT/XOR/MUX/OR/AND/CONST cells: rem=0, quo=0; for i = width-1 .. 0: rem_in = (rem << 1) | ((a >> i) & 1) ge = !(rem_in < b) rem = ge ? rem_in - b : rem_in quo = quo | (ge << i) The result is a pure combinational network the gate-level sim (nx_nxgate_sim) can verify 1:1 against behavioral a/b -- so the loop can PROVE a correct divider replaces the stub, not just CATCH the stub. (Operands assumed non-negative + small enough that signed LT == unsigned compare; the full 64-bit unsigned compare is a later widening, mechanical.) This is a gate-network GENERATOR -- parameterised by width, it emits the divider; that is the "invention" artifact, distinct from a hand-built netlist. license_tier: ORIGINAL