code wiki / _hdl_build / nx_alu_divider_r4_test.nx

nx_alu_divider_r4_test.nx

buildroot/runtime/_hdl_build/nx_alu_divider_r4_test.nx

3148 B75 linesdepth 9pulls 9 transitivereach 0 importersview sourcekind gate/prooftopic alu
docsdependenciesstructsconstsfunctions

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nx_alu_divider_r4_test.nx -- the divider's FULL qual+quant exceed proof. QUAL: radix-4 divider exhaustively correct over the whole 8-bit space. QUANT: radix-4 has FEWER subtract-stages than radix-2 (measured from the netlist by counting SUB cells = the sequential remainder-update depth). A full S-class exceed = BOTH (faster AND still 100%-correct). Honest scope: this is the STAGE-COUNT (iteration-latency) quant win; the further SRT carry-save (no carry-propagate add in the loop) win is a later step. Known answer (FAIL LOUD): "65280 65280 4 8 " = ok, total, r4_subtract_stages, r2_subtract_stages. exit 0 iff 100%-correct AND r4_subs < r2_subs.

dependencies 1 imports · 0 importers

nx_alu_divider_r4.nx nx_alu_divider_r4_test.nx

imports: nx_alu_divider_r4.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main nx_div_synth_r4 div_const div_op2 div_mux count_kind nx_gsim_run nx_gsim_kind_supported nx_gsim_eval_cell nx_div_synth nx_sink_init_mem nx_div_synth_sink nx_sink_const nx_hdl_wire nx_hdl_signal_alloc nx_hdl_kind_is_valid nx_hdl_width_is_valid nx_sink_cell nx_hdl_wire ↻ sys_mmap _emit_num _nl

structs

none

consts

none

functions

14func _emit_num(v: i64) -> i64
called by 1: main
22func _nl() -> i64 { let z: *u8 = sys_mmap(2); z[0] = 10; sys_write(1, z, 1); return 0 }
called by 1: main
24func count_kind(g: *NxGsim, kind: i64) -> i64
called by 1: main
31func main() -> i64