nx_alu_netlist_build_div.nx

nx_alu_netlist_build_div.nx -- the ALU op-select netlist with the PROVEN restoring divider (nx_div_synth) wired into the DIV/DIVU/REM/REMU subnets, in place of the ADD stub. This is the loop's FIRST hardware invention COMPOSED into context: the Generator (nx_div_synth) emits a divider gate- network, the Verifier (nx_gsim_run) proves it matches behavioral div/rem INSIDE the full ALU op-select cascade -- not just in isolation. Same topology as nx_alu_netlist_build (CONST opcode + subnet + EQ match; cascade MUX), built in nx_nxgate_sim's append convention (div_const/div_op2/ div_mux from nx_alu_divider.nx) so the divider sub-network slots in directly. Non-div ops still use the SINGLE-SOURCE nx_alu_op_to_gate_kind (one cell). DIV/DIVU take the divider's quotient; REM/REMU take its remainder. Width 64 (full RV64). Operands assumed non-negative + small enough that the signed LT in the restoring loop equals the unsigned compare -- the documented V1 envelope of nx_div_synth; the full 64-bit unsigned widening is mechanical.