nx_alu_netlist_build.nx

nx_alu_netlist_build.nx -- builds the ALU op-select netlist IN MEMORY as the ONE source the gate-sim (nx_nxgate_sim.nx) verifies. Mirrors synth_emit_alu_gates.nx's topology exactly: per op K in 1..NX_RV64IM_ALU_N-1: CONST(K) opcode literal subnet = KIND(a, b) KIND = nx_alu_op_to_gate_kind(K) <-- SHARED match = EQ(op_in, CONST(K)) cascade: prev0 = CONST(0) the INVALID branch prev = MUX(match_K, subnet_K, prev) for K = 1..N-1 result = last MUX fanout Because the per-op subnet KIND comes from the SAME nx_alu_op_to_gate_kind the text emitter uses, nx_gsim_run over this netlist verifies the emitter's ACTUAL op->kind decisions. This is the SIL-3 closure: one source, two consumers (text serializer + functional sim), no hand-kept copy. Cells are emitted in topological order (every fanin net is driven by an earlier cell), which nx_gsim_run (combinational, single forward pass) needs. Caller allocates cells[] (>= 128 NxGsimCell) and a vals[] net array (>= n_nets i64). Net ids 0/1/2 are reserved for a / b / op_in primary inputs.