nx_alu_netlist_full_test.nx

nx_alu_netlist_full_test.nx -- SIL-3 VERIFIER over the FULL 29-op ALU. Builds the ALU op-select netlist via nx_alu_netlist_build (the ONE source the text emitter also derives from), then for EVERY op K in 1..28 runs the gate-level functional sim and diffs vs the behavioral oracle nx_rv64im_alu_compute(K, a, b). This is the closure of "consume the ACTUAL emitter topology + diff vs behavioral over all 29 ops": where the seed emitter is faithful the sim MATCHES; where it stubs (DIV/REM->ADD, mulh->MUL) the sim DIVERGES -- the verifier CATCHES every silent gate-emit hole, not just DIV. That divergence set is the 5W1H feedback the Generator consumes. a=20 b=4. Known answer (FAIL LOUD): "covered=28 match=17 diverge=11" rc=0. 17 faithful: ADD SUB AND OR XOR SLL SRL SRA SLT SLTU MUL ADDW SUBW SLLW SRLW SRAW MULW (all single-cell ops the seed lowers exactly) 11 holes: MULH MULHSU MULHU (low-product MUL, want high) + DIV DIVU REM REMU DIVW DIVUW REMW REMUW (ADD stub, want divider) When a real divider sub-network replaces the DIV stub in nx_alu_op_to_gate_kind, this same gate flips DIV from DIVERGE to MATCH -- the first HW invention.