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nx_alu_divider_alu_test.nx
buildroot/runtime/_hdl_build/nx_alu_divider_alu_test.nx
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nx_alu_divider_alu_test.nx -- HARDWARE INVENTIONS verified IN the ALU. Builds
the ALU op-select netlist with the proven restoring divider (nx_div_synth)
wired into DIV/DIVU/REM/REMU AND the proven wide multiplier (nx_mul_wide) wired
into MULH/MULHSU/MULHU (high-product + sign corrections), then censuses every
op vs the behavioral oracle nx_rv64im_alu_compute. Compared to the stub census
(gate_nx_alu_netlist_full = match 17 / diverge 11), seven ops FLIP to MATCH:
the Verifier PROVES the divider + the mulh high-product replaced the stubs,
gate-level, inside the full ALU.
a=20 b=4. Known answer (FAIL LOUD): "covered=28 match=28 diverge=0" rc=0 --
the FULL RV64IM ALU verified gate-level, ZERO holes. All 28 ops match behavioral:
the divider (DIV/DIVU/REM/REMU), the wide-mul high-product (MULH/MULHSU/MULHU),
and the 32-bit W-variants (DIVUW/REMUW/DIVW/REMW, mask->32-bit divide->sext32,
signed via abs+sign-correct). Hardened: divider 5 vectors, mulh 5 (neg/max),
W-unsigned 5 (large/sext/div0), W-signed 6 (all sign combos + INT_MIN/-1 + div0).
dependencies 2 imports · 0 importers
imports: nx_alu_netlist_build_div.nxrv64im_min_alu.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 20 | func _emit_cstr(s: *u8) -> i64 called by 1: main |
| 27 | func _emit_dec(v: i64) -> i64 called by 1: main |
| 42 | func _div_check(g: *NxGsim, info: *NxAluNetlist, a: i64, b: i64, op: i64) -> i64 |
| 53 | func main() -> i64 |