nx_alu_divider_race_test.nx

nx_alu_divider_race_test.nx -- the RACE step (theory -> proof -> RACED). Not a correctness test: it MEASURES our divider's latency/area from the netlist and races it against the RESEARCH algorithm ladder. "How fast vs what exists." Digit-recurrence dividers are dominated by LATENCY = #sequential stages (the remainder dependency chain). Research ladder (stages for a W-bit divide): restoring / non-restoring (radix-2): W [the floor] radix-4 SRT: ceil(W/2) [~2x] Goldschmidt / Newton (multiplicative): ceil(log2 W) [the FRONTIER, quadratic] We MACHINE-COUNT our radix-2 and radix-4 stages (= SUB cells) + total cells (area proxy) and print them next to the ladder, with the HONEST verdict. HONEST scope: a gate-level structural race (stages/gates = what DETERMINES eventual latency/area); a true ns/cycle race vs a synthesized incumbent needs place-&-route/silicon (the L8 gap). Output (FAIL LOUD on a measurement error): "<r2_stages> <r2_cells> <r4_stages> <r4_cells> <goldschmidt_frontier>".