nx_recip_synth.nx

nx_recip_synth.nx -- the MULTIPLICATIVE (Newton-Raphson reciprocal) divider instantiated as an NxGsim GATE-NETWORK (the gate-network instantiation of the algorithm proven scalar in nx_alu_divider_newton.nx, maxcorr=1). This is the "first provable rung" (W=16): the SAME Newton math as the scalar proof, emitted as a pure combinational word-level netlist using ONLY the already-proven cell builders div_const / div_op2 / div_mux (nx_alu_divider.nx) over the gate-sim's MUL/SHL/SHR/SUB/ADD/LTU/XOR/AND/OR/MUX/CONST cells. WHY W=16 is the smallest GATE-NETWORK-provable variant: At W=16 every intermediate fits i64 with a PLAIN depth-1 MUL cell, so NO nx_mul_wide (128-bit organ) is needed -- verified bit-widths (D<=2^16): dn <= 2^16 (17b) dn*x = dx <= 2^33 (34b) 2F^2-dx = t <= 2^33 (34b) x*t <= 2^49 (49b) N*x <= 2^33 (34b) all <= 49 bits, so a single MUL cell (low 64 bits, no wrap) is EXACT here. The new code is therefore just the gate-emitter wrapper around 100%-proven math + proven cells -- no new unproven gate organ is exercised. The nx_mul_wide-dependent rungs (W>=24, x*t=73b) are the next milestone. data-dependent normalization (msb_pos / barrel-shift) is BUILT IN GATES here: - msb_synth : priority encoder over a runtime net (cascade of LTU/MUX), returns p with 2^p <= D < 2^(p+1) for D in [1, 2^16). - barrel SHL/SHR by a *net* count uses the sim's SHL/SHR cells directly (the cell takes b = the runtime shift-count net), so normalization Dn = D<<s and extraction (N*x)>>(17+p) are pure gates. The correction tail is UNROLLED to a fixed KCORR (data-INDEPENDENT, so the latency stays O(iters)+O(1)); the scalar proof showed maxcorr=1, so KCORR=2 is a safe constant. license_tier: ORIGINAL HONEST-METRIC NOTE (do not fool ourselves): nx_nxgate_sim assigns depth-1 to every word-level cell, so a MUL cell looks as cheap as an AND. This proves FUNCTIONAL 1:1 correctness of the gate-network, and the iteration COUNT (3 vs W=16 restoring stages) is a real cell-count/sequential-step win -- but NOT a true critical-path latency exceed until a real gate-delay model exists.