synth_emit_regfile_gates.nx

synth_emit_regfile_gates.nx -- per-module register-file emitter for .nxgate. SECOND per-RTL-module emitter in the SOVEREIGN canonical chain (after synth_emit_alu_gates.nx). Emits the .nxgate gate netlist for rv64im_min_regfile.nx: a 31-deep D-flip-flop bank (x1..x31; x0 is hardwired zero) with one write port and two combinational read ports. This is the FIRST emitter to exercise the SEQUENTIAL (.FLOP) half of the .nxgate format -- synth_emit_alu_gates.nx was purely combinational (no clocked storage). It also exercises AND-gating (write-enable) which the ALU cascade never used. Gate structure (matches every in-order RV64 core: SiFive E2 .. Rocket): x0: constant 0 (no flop; reads return 0, writes drop) x1..x31 each: q_i = DFF(d_i, clk, rst) ; rst -> 0 d_i = MUX(we_i, q_i, rd_value) ; hold unless written we_i = AND(write_en, (rd_idx == i)) rs1_data = 32:1 read cascade: (rs1_idx == i) ? q_i : prev (seed = 0) rs2_data = 32:1 read cascade: (rs2_idx == i) ? q_i : prev (seed = 0) The per-index 5-bit constant is SHARED across the write match and both read matches (one .CONST per register, not three). Net-linkage conventions (TIGHTER than synth_emit_alu_gates.nx; see the RECONCILE block at the end of this file): 1. Every internal net gets an explicit `.NET <id> width=<W>` line so the netlist is width-complete. The ALU seed referenced cell-output nets that were never declared with a width. 2. `.CONST <netid> width value` uses the NET handle as its id, so the constant net is self-consistently linked to its consumers (the ALU seed used a running cell id that no fanin referenced). 3. MUX fanin order follows the .nxgate spec verbatim: (sel, in0, in1) where in0 is the sel==0 value, in1 the sel==1 value. (out = sel ? in1 : in0.) Status: SEED. 2026-05-28. Covers all 31 writable regs + x0-zero + dual read. Verified structurally by synth_emit_regfile_gates_smoke.nx (port/flop/cell/const/net counts + format markers + all-OK verdicts). Functional gate-sim equivalence vs the behavioural regfile awaits