code wiki / _hdl_build / nx_fpga_cpu7_gate.nx

nx_fpga_cpu7_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_cpu7_gate.nx

8251 B121 linesdepth 7pulls 16 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 9 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_ram.nx nx_fpga_decode.nx nx_fpga_alu.nx nx_fpga_regfile.nx nx_fpga_pc.nx rv64im_min_alu.nx nx_syscalls.nx nx_fpga_cpu7_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_ram.nxnx_fpga_decode.nxnx_fpga_alu.nxnx_fpga_regfile.nxnx_fpga_pc.nxrv64im_min_alu.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap seq_build_ram fl_gate_to_lut4 fl_gate_ref lut4_index ram_addr_inputs ram_ncells fab_build_decode r9_sub r9_msel0 r9_msel1 r9_right r9_arith r9_uns r9_class sys_mmap ↻ fab_build_alu fl_gate_to_lut4 ↻ fab_parity3_init fab_maj3_init seq_build_regfile fl_gate_to_lut4 ↻ rf_addr_inputs rf_ncells seq_build_pc fl_gate_to_lut4 ↻ pc_ncells enc_i enc_r ram_write seq_tick seq_eval fab_resolve lut4_eval lut4_index ↻ sys_mmap ↻ fab_resolve ↻

structs

none

consts

none

functions

20func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
22func enc_i(rd: i64, rs1: i64, imm: i64, f3: i64) -> i64 { return ((imm & 4095) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 19 }
called by 1: main
23func enc_r(rd: i64, rs1: i64, rs2: i64, f3: i64) -> i64 { return (rs2<<20)|(rs1<<15)|(f3<<12)|(rd<<7)|51 }
25func main() -> i64