nx_fpga_adder.nx

nx_fpga_adder.nx -- LIB: RUNG 6 of the sovereign FPGA-boot sim -- TECH-MAP a WIDE gate into a LUT4 NETWORK. The R4 tech-map covered only single-LUT primitives; a real CPU's ALU is WIDE (64-bit ADD/SUB/compare). This rung decomposes an N-bit ADD into a fabric of LUT4 cells: a ripple-carry chain of full-adders, one sum-LUT (parity3) + one carry-LUT (maj3) per bit, with the carry wired bit-to-bit (the routing). The emitted fabric runs on fab_eval (rung 5) driven ONLY by its bitstream. This is the bridge to running the actual rv64im ALU netlist on the simulated fabric (rung 9). Builds on nx_fpga_fabric / nx_fpga_lut. FABRIC LAYOUT for width W (npi = 2W+1): PI 0..W-1 = a bits, PI W..2W-1 = b bits, PI 2W = carry-in. cell 2i = SUM bit i (LUT init = parity3 of a_i,b_i,carry_i) cell 2i+1 = CARRY bit i (LUT init = maj3 of a_i,b_i,carry_i) carry_i source: i==0 -> PI(2W) (cin); else -> cell (2i-1) output (prev bit's carry) [topologically sorted] POs: po_src[i]=npi+2i (sum bit i, i=0..W-1); po_src[W]=npi+(2W-1) (final carry-out) NEVER-BRICK (#26): pure integer, bounded (2W cells), total, deterministic, zero hardware-state writes. license_tier: ORIGINAL