nx_fpga_addsub.nx

nx_fpga_addsub.nx -- LIB: the FPGA ALU ARITHMETIC UNIT (ADD/SUB, op-selected) as a LUT4 fabric. Extends the rung-6 ripple adder with OP-SELECTION -- the essence of an ALU. Two's-complement trick: a - b = a + (~b) + 1, so a single control bit `sub` drives BOTH a per-bit XOR (invert b when sub=1) AND the carry-in (cin=sub): sub=0 -> b XOR 0 = b, cin=0 -> a + b sub=1 -> b XOR 1 = ~b, cin=1 -> a + ~b + 1 = a - b (mod 2^W) All on the fabric, run from its bitstream via fab_eval. The bridge from "the adder runs on the fabric" to "an op-SELECTED ALU runs on the fabric" -> the rv64 ALU on the simulated FPGA (rung 9). FABRIC LAYOUT width W (npi = 2W+1): PI 0..W-1 = a, PI W..2W-1 = b, PI 2W = sub(control). cells 0..W-1 : bxor_i = b_i XOR sub (XOR LUT) cells W..3W-1 : ripple adder over a_i + bxor_i with carry_0 = sub (parity3 sum + maj3 carry per bit) POs: po_src[i] = npi + (W + 2i) = sum bit i (i=0..W-1) -- the W-bit result a +/- b ncells = 3W, npo = W. NEVER-BRICK (#26): pure integer, bounded, total, deterministic, zero hardware writes. license_tier: ORIGINAL