nx_fpga_alu.nx

nx_fpga_alu.nx -- LIB: RUNG 8 -- the LOGIC+ARITHMETIC ALU DATAPATH on the LUT4 fabric, op-selected by a per-bit result-MUX. Computes a/b -> {AND, OR, XOR, ADD, SUB} and selects one via control bits, ALL on the fabric (run from its bitstream by fab_eval). Verified (in the gate) against the team's behavioral nx_rv64im_alu_compute at the full 64-bit RV64 word width. This is the datapath; the op->control DECODE is the control unit (rung 9). Shifts/compares/mul/div are follow-on rungs (barrel-shifter / borrow-logic / multiplier-tree LUT networks). Builds on nx_fpga_addsub / nx_fpga_adder / nx_fpga_fabric / nx_fpga_lut. CONTROL INPUTS (decoded per op by the caller): sub (add/sub), msel0/msel1 (2-bit result select): msel1=0,msel0=0 -> AND msel1=0,msel0=1 -> OR msel1=1,msel0=0 -> XOR msel1=1,msel0=1 -> ARITH(=add/sub) ARITH op: sub=0 -> a+b, sub=1 -> a-b (two's complement, the rung-7 unit). FABRIC LAYOUT width W (npi = 2W+3): PI 0..W-1=a, W..2W-1=b, 2W=sub, 2W+1=msel0, 2W+2=msel1. ncells = 9W: [0,W) AND_i [W,2W) OR_i [2W,3W) XOR_i [3W,4W) bxor_i=XOR(b_i,sub) [4W,6W) ripple adder over a_i+bxor_i (cin=sub): sum cell 4W+2i = arith_i, carry cell 4W+2i+1 [6W,9W) per-bit result MUX (3 cells/bit): m_lo=MUX(msel0,AND,OR), m_hi=MUX(msel0,XOR,arith), res=MUX(msel1,m_lo,m_hi) POs: po_src[i] = res cell of bit i (= the selected op's bit i) NEVER-BRICK (#26): pure integer, bounded (9W cells), total, deterministic, zero hardware-state writes. license_tier: ORIGINAL