nx_fpga_lut.nx

nx_fpga_lut.nx -- LIB: RUNG 4 of the sovereign FPGA-boot SIMULATOR (operator 2026-06-22: "for the fpga if there is a way to simulate it lets build that from the hardware rung up on specs"). The FPGA's ATOM is the 4-input Look-Up Table (LUT4): 16 SRAM config bits that, loaded by the bitstream, make ONE cell compute ANY boolean function of 4 inputs. This lib models the LUT4 + DFF fabric primitives PER SPEC and the TECH-MAP that compiles the team's gate-netlist primitives (nishi_synth_gates NX_GATE_KIND_*) into LUT4 init bits = the per-LUT bitstream. This is the bedrock the higher rungs (place -> route -> bitstream -> fabric-config-sim -> boot) stack on. Built on the VERIFIED lower rungs: rv64im_min_sim (behavioral), synth_emit_alu_gates (netlist), nx_nxgate_sim (gate eval). NEVER-BRICK (#26) BY CONSTRUCTION: pure integer, NO float, NO syscall that writes any real/persistent hardware state -- a LUT is evaluated in memory. Bounded (a LUT4 has exactly 16 input combinations), total (every input yields 0/1), deterministic (same input -> same bit). A simulator cannot brick anything; the gate asserts these. Kind codes MIRROR nishi_synth_gates.nx (sealed enum) so the tech-map is over the SAME primitives the netlist emitter uses (local consts avoid dragging that file's heavy hdl-primitive deps; codes are a stable sealed set). license_tier: ORIGINAL