nx_nbit.nx

nx_nbit.nx -- LIB: NHDL H5 -- sovereign PLACE-and-ROUTE + BITSTREAM for the VIRTUAL FPGA (the nextpnr/prjtrellis competitor). H4 synthesizes a logical netlist (cells + nets); this is the BACK-END that maps it onto a PHYSICAL 2-D grid of LUT tiles (PLACEMENT) with inputs addressed by grid coordinate (ROUTING), serializes a sovereign BITSTREAM (our own, like prjtrellis is for ECP5), and the VIRTUAL FPGA loads + evaluates it. The placement is a real permutation (column-major), so correctness proves routing follows arbitrary placement -- not a relabel. "Simulate the chip+board BEFORE buying": the whole RTL->synth->P&R->bitstream->virtual-board chain runs in-sim. NEVER-BRICK (#26): pure memory, bounded, deterministic, zero hardware-state writes. license_tier: ORIGINAL HONEST scope: 1 LUT/tile, full routability assumed (every tile reachable). The CONSTRAINED-routing optimization (limited channels + simulated annealing -- nextpnr's hard part) is the depth rung; this proves the P&R DATA FLOW (place -> route -> bitstream -> virtual eval == netlist) sovereignly + correctness-preservingly.