nx_nhdl.nx

nx_nhdl.nx -- LIB: NHDL H1 -- the sovereign Nishi netlist format (a Verilog COMPETITOR, not a Verilog emit). Operator 2026-06-26: "verilog should only be a benchmark build our own verilog competitor in nishi ecosystem from the hardware rung up each rung." So instead of serializing our LUT4/DFF fabric to third-party Verilog (now a benchmark yardstick only), this is OUR OWN textual netlist interchange format -- flat, instance-based (cells=instances, nets=wires; the canonical netlist structure per the researched Wikipedia 'Netlist' entry: a header + a per-instance table, one line per entry, space-separated fields). Designed to round-trip the fabric byte-exact AND to be far more compact than Verilog's verbose `assign comb[k]=(INIT>>(...))&1; //@C...`. GRAMMAR (v1): .nhdl 1 .module <name> <npi> <npo> <ncells> L <init> <s0> <s1> <s2> <s3> # a LUT4 cell (combinational): 16-bit init + 4 input nets D <dsrc> # a DFF cell (sequential): the D-input net (init unused, Q is caller state) ... (ncells lines, in cell-index order; net s<npi => primary input s, else cell (s-npi)'s output) .po <net0> <net1> ... <net_{npo-1}> .end NEVER-BRICK (#26): pure text emit/parse, bounded, deterministic, zero hardware-state writes. license_tier: ORIGINAL