nx_nrtl.nx

nx_nrtl.nx -- LIB: NHDL H3+H4 -- sovereign RTL + SYNTHESIS (the Yosys competitor). H1/H2 gave a netlist format + hierarchy that you EMIT from a fabric; this is the layer you AUTHOR in: a tiny RTL where you write bus-level equations, and a SYNTHESIZER that LOWERS them to the LUT4 fabric -- reusing the proven fabric builders (ripple adder, per-bit logic LUTs) + fab_append (R32a) to compose. Author 3 lines of RTL -> a 32-gate netlist, sovereignly. NRTL GRAMMAR (v1): single-char bus names (a,b,t,u,y...), 3-address combinational statements. .nrtl 1 .module <name> <W> # bus width W .in a b # input buses (each W bits; assigned PI nets in order) .out y # the output bus t = a & b # one binary op per statement: & (AND) | (OR) ^ (XOR) + (ADD), bit-parallel @ W u = a ^ b y = t + u .end SYNTHESIS: each statement -> build the op's fabric sub-network (logic LUTs or the ripple adder), fab_append it wiring its inputs to the operand buses' nets; the result bus = the appended outputs. The output bus -> the POs. NEVER-BRICK (#26): pure memory, bounded, deterministic, zero hardware-state writes. license_tier: ORIGINAL