nx_fpga_compose.nx

nx_fpga_compose.nx -- LIB: RUNG 32a -- COMPOSE separate module-fabrics into ONE unified fabric. The CPU rungs (R11..R20) build SEPARATE fabrics (decode, ALU, regfile, PC, IMEM/DMEM RAM) and wire them together in host NishiLang per clock step. To emit the WHOLE CPU as ONE Yosys-synthesizable Verilog netlist (R29 emitted only the ALU) -- the artifact nextpnr/prjtrellis consume toward an ECP5 bitstream -- the datapath must BE a single composed fabric. fab_append copies a sub-fabric's cells into a growing composed fabric, REMAPPING every net: a sub-fabric cell ref (s >= snpi) -> the composed cell slot it landed in; a sub-fabric PI ref (s < snpi) -> the composed net it is WIRED to (inmap[s], either a composed PI or a prior sub-fabric's output). LUT (kind 0) and DFF (kind 1) cells are copied uniformly, so sequential state (regfile/PC/RAM) composes exactly like combinational logic. The composed fabric runs unchanged on fab_eval / seq_eval / seq_tick and serializes through nx_fpga_verilog. NEVER-BRICK (#26): pure memory, bounded by total cells, deterministic (same inputs -> same netlist), zero hardware-state writes. license_tier: ORIGINAL