code wiki / _hdl_build / nx_fpga_compose_gate.nx

nx_fpga_compose_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_compose_gate.nx

7604 B123 linesdepth 5pulls 9 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 7 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_compose.nx nx_fpga_adder.nx nx_fpga_verilog.nx nx_fpga_fabric.nx nx_syscalls.nx nx_fpga_compose_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_compose.nxnx_fpga_adder.nxnx_fpga_verilog.nxnx_fpga_fabric.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap build_compose sys_mmap ↻ fab_build_ripple_adder fab_parity3_init fab_maj3_init fab_append fab_sub_out run_compose fab_eval fab_resolve lut4_eval lut4_index fab_resolve ↻ gn fab_emit_verilog_seq vlg_wr_str vlg_wr_int sys_mmap ↻ vlg_wr_op vlg_wr_str ↻ vlg_wr_int ↻ sys_exit

structs

none

consts

none

functions

18func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
22func build_compose(W: i64, cinit: *i64, csrc: *i64, ckind: *i64, cpo: *i64, outnpi: *i64) -> i64
49func run_compose(W: i64, NCELLS: i64, NPI: i64, cinit: *i64, csrc: *i64, cpo: *i64, pi: *i64, co: *i64, a: i64, b: i64, c: i64) -> i64
59func main() -> i64