nx_fpga_verilog.nx

nx_fpga_verilog.nx -- LIB: RUNG 28 -- the SYNTH BRIDGE emitter, SEQUENTIAL-capable. Serializes any fabric (combinational LUT4 cells AND clocked DFF cells, the `kind` bitstream from nx_fpga_seq) to a Yosys-synthesizable Verilog gate-netlist: LUT cells -> combinational `assign comb[k] = (INIT >> inputs) & 1`; DFF cells -> a `reg ff[k]` latched in `always @(posedge clk)`. Each cell carries a machine-readable `//@C k kind init s0 s1 s2 s3` tag so the netlist round-trips (fab_parse_seq reconstructs kind/init/src/po byte-identically). This is the layer nishi_hdl_primitives calls "future" and rv64im_min leaves undone -- the path from the sim fabric toward an ECP5 bitstream. NEVER-BRICK (#26): pure text emit/parse, bounded, deterministic, zero hardware-state writes. license_tier: ORIGINAL