code wiki / _hdl_build / nx_nrtl_gate.nx

nx_nrtl_gate.nx

buildroot/runtime/_hdl_build/nx_nrtl_gate.nx

5528 B86 linesdepth 6pulls 11 transitivereach 0 importersview sourcekind gate/prooftopic nrtl
docsdependenciesstructsconstsfunctions

dependencies 7 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_nrtl.nx nx_nhdl.nx nx_fpga_verilog.nx nx_fpga_fabric.nx nx_syscalls.nx nx_nrtl_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_nrtl.nxnx_nhdl.nxnx_fpga_verilog.nxnx_fpga_fabric.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap nrtl_synth sys_mmap ↻ nh_skip_word nh_skip_ws nh_isws nh_isws ↻ nh_rd_int nh_skip_ws ↻ nh_isdig nh_skip_ws ↻ nr_rdc nh_skip_ws ↻ fab_build_ripple_adder fab_parity3_init fab_maj3_init fab_append fab_sub_out build_bitop fl_gate_to_lut4 fl_gate_ref lut4_index run2 fab_eval fab_resolve lut4_eval lut4_index ↻ fab_resolve ↻ gn nhdl_emit nh_ws nh_wi sys_mmap ↻ fab_emit_verilog_seq vlg_wr_str vlg_wr_int sys_mmap ↻

structs

none

consts

none

functions

17func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
20func run2(cn: i64, NPI: i64, cinit: *i64, csrc: *i64, cpo: *i64, pi: *i64, co: *i64, W: i64, a: i64, b: i64) -> i64
28func main() -> i64