nx_fpga_fabric.nx

nx_fpga_fabric.nx -- LIB: RUNG 5 of the sovereign FPGA-boot sim. A FABRIC is an array of LUT4 cells wired together by ROUTING; a BITSTREAM is (per-cell LUT init + per-input wire source). fabric_eval executes the fabric driven ONLY by the bitstream -- exactly what a real FPGA does after configuration: it no longer knows the source netlist, only the loaded SRAM bits. This is the leap from "one LUT" (rung 4) to "a configured fabric computes a real multi-gate circuit." Builds on nx_fpga_lut (lut4_eval). WIRE SOURCE ENCODING (the routing): an input source `s` is a primary-input index if s < npi, else it is the output of cell (s - npi). Cells are evaluated in index order, so a topologically-sorted fabric (cell k only wires from PIs or cells < k) is a single forward pass -- no comb loop (and the gate proves outputs are total). BITSTREAM layout (flat i64 arrays, caller-owned -- never-brick #26: pure memory, no real hardware write): ncells, npi init[k] 16-bit LUT SRAM for cell k src[k*4 + 0..3] the 4 input wire sources for cell k npo, po_src[p] each primary output's wire source license_tier: ORIGINAL