nx_fpga_seq.nx

nx_fpga_seq.nx -- LIB: RUNG 10a -- the SEQUENTIAL (clocked, stateful) fabric. Every prior rung is purely COMBINATIONAL (fab_eval = one forward pass, no memory). A real CPU is SEQUENTIAL: registers and a program counter that HOLD state across clock cycles. This adds the DFF (the FPGA's sequential atom) to the fabric: a cell can be a LUT4 (combinational) or a DFF (holds Q, latches D on a clock TICK). seq_eval settles the combinational logic (DFFs output their CURRENT Q); seq_tick settles then latches every DFF's D->Q SIMULTANEOUSLY (no race). Feedback through a DFF is legal (q -> +1 -> D) -- that is exactly a counter / program counter. REPRESENTATION (adds `kind` to the bitstream): kind[k] 0=LUT4, 1=DFF. LUT cell: init[k] + src[k*4+0..3] inputs. DFF cell: src[k*4+0] = D source (init unused); q[k] = held state (caller-owned, initialized by the caller). NEVER-BRICK (#26): state is bounded (caller-owned q[]), tick is bounded (ncells), deterministic (same q+inputs -> same next q), zero hardware-state writes. Builds on nx_fpga_lut (lut4_eval) + nx_fpga_fabric (fab_resolve). license_tier: ORIGINAL