topic: fpga
58 modules sharing the fpga name family (derived from the tree's prefix discipline).
The 'fpga' topic family in the Nishi sovereign ecosystem provides foundational components for FPGA boot simulation and logic implementation within the LUT4 fabric. Modules like nx_fpga_adder and nx_fpga_addsub demonstrate arithmetic operations, while nx_fpga_alu integrates logic and arithmetic functions. These modules collectively enable the construction of complex datapaths and ALU units, supporting the broader FPGA-BOOT-SIM capabilities. The nx_fpga_bitstream and related modules facilitate the encoding and management of bitstream data, essential for configuring and deploying FPGA designs within the sovereign architecture.
auto-narrated by the local model from this topic's module headers; links verified against the wiki index.
narrated overview -- maintained by the narration lane, module links verified against this wiki.
| module | description | lines | funcs |
|---|---|---|---|
| nx_fpga_adder.nx | LIB: RUNG 6 of the sovereign FPGA-boot sim -- TECH-MAP a WIDE gate into a LUT4 NETWORK. | 80 | 5 |
| nx_fpga_adder_gate.nx | 164 | 3 | |
| nx_fpga_addsub.nx | LIB: the FPGA ALU ARITHMETIC UNIT (ADD/SUB, op-selected) as a LUT4 fabric. Extends the | 67 | 2 |
| nx_fpga_addsub_gate.nx | 150 | 3 | |
| nx_fpga_alu.nx | LIB: RUNG 8 -- the LOGIC+ARITHMETIC ALU DATAPATH on the LUT4 fabric, op-selected by a | 88 | 2 |
| nx_fpga_alu_gate.nx | 140 | 2 | |
| nx_fpga_alu_verilog_gate.nx | 83 | 2 | |
| nx_fpga_bitstream.nx | LIB: sovereign BITSTREAM ENCODER (omniforge SI M4 = the prjtrellis replacement, no Lattice | 73 | 5 |
| nx_fpga_bitstream_gate.nx | GATE for the sovereign bitstream encoder (M4 prjtrellis replacement). Encodes a real | 112 | 5 |
| nx_fpga_board_anim_gate.nx | 106 | 4 | |
| nx_fpga_board_gate.nx | 119 | 4 | |
| nx_fpga_boot_gate.nx | 153 | 8 | |
| nx_fpga_census.nx | the FPGA-BOOT-SIM capability census as a code-defined seed into the SOVEREIGN seg-store | 110 | 5 |
| nx_fpga_census_store.nx | LIB: the FPGA-BOOT-SIM capability census in the SOVEREIGN seg-store | 53 | 5 |
| nx_fpga_cmp.nx | LIB: RUNG 8b -- the ALU COMPARE ops (SLT signed, SLTU unsigned) on the LUT4 fabric. New | 80 | 2 |
| nx_fpga_cmp_gate.nx | 111 | 2 | |
| nx_fpga_compose.nx | LIB: RUNG 32a -- COMPOSE separate module-fabrics into ONE unified fabric. | 50 | 2 |
| nx_fpga_compose_gate.nx | 123 | 4 | |
| nx_fpga_counter_gate.nx | 99 | 3 | |
| nx_fpga_cpu2_gate.nx | 166 | 6 | |
| nx_fpga_cpu3_gate.nx | 199 | 8 | |
| nx_fpga_cpu4_gate.nx | 151 | 8 | |
| nx_fpga_cpu5_gate.nx | 131 | 6 | |
| nx_fpga_cpu6_gate.nx | 181 | 11 | |
| nx_fpga_cpu7_gate.nx | 121 | 4 | |
| nx_fpga_cpu8_gate.nx | 138 | 6 | |
| nx_fpga_cpu9_gate.nx | 153 | 8 | |
| nx_fpga_cpu_dc_gate.nx | 187 | 4 | |
| nx_fpga_cpu_gate.nx | 172 | 5 | |
| nx_fpga_dc.nx | LIB: RUNG 30 of the sovereign FPGA-boot sim -- the DISPLAY-CONTROLLER peripheral | 120 | 6 |
| nx_fpga_dc_gate.nx | 128 | 3 | |
| nx_fpga_decode.nx | LIB: RUNG 9 -- the RV64I R-type DECODER on the LUT4 fabric: maps (funct3, funct7 bit 5) | 65 | 9 |
| nx_fpga_div_gate.nx | 85 | 2 | |
| nx_fpga_ecall_gate.nx | 133 | 6 | |
| nx_fpga_fabric.nx | LIB: RUNG 5 of the sovereign FPGA-boot sim. A FABRIC is an array of LUT4 cells wired | 49 | 4 |
| nx_fpga_fabric_gate.nx | 119 | 4 | |
| nx_fpga_lui_gate.nx | 85 | 4 | |
| nx_fpga_lut.nx | LIB: RUNG 4 of the sovereign FPGA-boot SIMULATOR (operator 2026-06-22: "for the fpga if | 94 | 6 |
| nx_fpga_lut_gate.nx | 105 | 2 | |
| nx_fpga_mul_gate.nx | 82 | 2 | |
| nx_fpga_pc.nx | LIB: RUNG 13a -- the PROGRAM COUNTER as a LOADABLE fabric register (the control-flow atom). | 67 | 4 |
| nx_fpga_pc_gate.nx | 69 | 2 | |
| nx_fpga_pnr.nx | LIB: sovereign PLACE-AND-ROUTE (omniforge SI M4, the nextpnr replacement) for the LUT4 | 240 | 5 |
| nx_fpga_pnr_gate.nx | 151 | 5 | |
| nx_fpga_ram.nx | LIB: RUNG 17 -- a true RAM fabric on the SEQUENTIAL fabric. Same structure as the register file | 138 | 5 |
| nx_fpga_ram_gate.nx | 63 | 3 | |
| nx_fpga_regfile.nx | LIB: RUNG 10 -- a REGISTER FILE on the SEQUENTIAL fabric (the core CPU storage). R | 140 | 5 |
| nx_fpga_regfile_gate.nx | 112 | 2 | |
| nx_fpga_rexec.nx | LIB: RUNG 32b -- the R-type ALU-class EXECUTE datapath as ONE composed fabric. | 59 | 2 |
| nx_fpga_rexec_gate.nx | 125 | 3 | |
| nx_fpga_rtype_gate.nx | 159 | 4 | |
| nx_fpga_sdiv_gate.nx | 90 | 2 | |
| nx_fpga_seq.nx | LIB: RUNG 10a -- the SEQUENTIAL (clocked, stateful) fabric. Every prior rung is purely | 74 | 3 |
| nx_fpga_shift.nx | LIB: RUNG 8c -- the ALU SHIFTS (SLL/SRL/SRA) as a BARREL SHIFTER on the LUT4 fabric. | 77 | 2 |
| nx_fpga_shift_gate.nx | 136 | 2 | |
| nx_fpga_verilog.nx | LIB: RUNG 28 -- the SYNTH BRIDGE emitter, SEQUENTIAL-capable. Serializes any fabric | 115 | 8 |
| nx_fpga_verilog_gate.nx | 174 | 11 | |
| nx_fpga_verilog_seq_gate.nx | 88 | 3 |