nx_fpga_ram.nx

nx_fpga_ram.nx -- LIB: RUNG 17 -- a true RAM fabric on the SEQUENTIAL fabric. Same structure as the register file (nx_fpga_regfile) -- R words x W bits of DFF state, an addressed clocked WRITE port + an addressed combinational READ port, LUT4 address decode -- BUT with NO hardwired address: EVERY word (including address 0) is writable and reads back what was written. That is the difference between a register file (x0 must read 0) and a memory (word 0 is just a word). This is what lets data live at address 0 AND lets instructions be FETCHED from a memory fabric. PIs (npi = 2*AB + W + 1): raddr[0..AB-1] | waddr[AB..2AB-1] | wdata[2AB..2AB+W-1] | we[2AB+W]. NEVER-BRICK (#26): bounded state (caller-owned q[]), bounded tick, deterministic, no hardware write. license_tier: ORIGINAL