code wiki / _hdl_build / nx_fpga_ram_gate.nx

nx_fpga_ram_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_ram_gate.nx

4187 B63 linesdepth 6pulls 8 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 4 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_ram.nx nx_syscalls.nx nx_fpga_ram_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_ram.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap seq_build_ram fl_gate_to_lut4 fl_gate_ref lut4_index ram_addr_inputs ram_ncells ram_write seq_tick seq_eval fab_resolve lut4_eval lut4_index ↻ sys_mmap ↻ fab_resolve ↻ ram_ncells ↻ val_of ram_read seq_eval ↻ ram_ncells ↻ fab_po fab_resolve ↻ gn sys_exit

structs

none

consts

none

functions

13func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
15func val_of(a: i64) -> i64 { return 100 + a*13 } // distinct, NONZERO at a=0 (=100)
17func main() -> i64