nx_fpga_ram_gate.nx source

1import "nx_gate_gn.nx" 2import "nx_gate_base.nx" 3// nx_fpga_ram_gate.nx -- GATE for RUNG 17: a true RAM fabric (nx_fpga_ram). Proves EVERY address -- INCLUDING 4// address 0 -- is writable and reads back what was written (a register file hardwires x0->0 and CANNOT). This is 5// the memory primitive that lets data live at address 0 and lets instructions be FETCHED from a memory fabric. 6// T1 write 8 distinct words to addresses 0..7, read all back == written (0 mismatches; address 0 holds a NONZERO). 7// T2 address 0 specifically: reads back its nonzero value AND is re-writable (the regfile-impossible case). 8// T3 NEVER-BRICK. T4 LIAR-KILL (corrupt word-0's D-feed MUX -> address-0 readback diverges). 9// expect_exit: 0 license_tier: ORIGINAL 10import "nx_fpga_ram.nx" 11import "nx_syscalls.nx" 12 13func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw(" 14" as *u8); return ok } 15func val_of(a: i64) -> i64 { return 100 + a*13 } // distinct, NONZERO at a=0 (=100) 16 17func main() -> i64 { 18 gw("=== nx_fpga_ram_gate: RUNG 17 -- a true RAM fabric (every address writable, address 0 included) ===\n" as *u8) 19 var pass: i64 = 0; var total: i64 = 0 20 let R: i64 = 8; let W: i64 = 32; let AB: i64 = 3 21 22 let kind: *i64=sys_mmap(8*1100) as *i64; let init: *i64=sys_mmap(8*1100) as *i64; let src: *i64=sys_mmap(8*4200) as *i64 23 let po: *i64=sys_mmap(8*40) as *i64; let pi: *i64=sys_mmap(8*48) as *i64; let co: *i64=sys_mmap(8*1100) as *i64; let q: *i64=sys_mmap(8*1100) as *i64 24 seq_build_ram(R, W, AB, kind, init, src, po) 25 let nc: i64 = ram_ncells(R, W) 26 var z: i64=0; while z<nc { q[z]=0; z=z+1 } 27 28 // T1: write 0..7, read all back 29 var a: i64 = 0 30 while a < R { ram_write(R,W,AB,kind,init,src,pi,co,q,a,val_of(a)); a = a + 1 } 31 var mism: i64 = 0 32 a = 0 33 while a < R { let got: i64 = ram_read(R,W,AB,kind,init,src,pi,co,q,po,a); if got != val_of(a) { mism = mism + 1 } a = a + 1 } 34 total=total+1; if mism==0 { pass=pass+1; gw(" [PASS] " as *u8) } else { gw(" [FAIL] " as *u8) } 35 gw("T1 wrote 8 distinct words to addresses 0..7, all read back == written, mismatches=" as *u8); gn(mism); gw("\n" as *u8) 36 37 // T2: address 0 -- the regfile-impossible case 38 let z0: i64 = ram_read(R,W,AB,kind,init,src,pi,co,q,po,0) 39 ram_write(R,W,AB,kind,init,src,pi,co,q,0,7777) // re-write address 0 40 let z0b: i64 = ram_read(R,W,AB,kind,init,src,pi,co,q,po,0) 41 total=total+1; var t2ok: i64=1; if z0!=100 {t2ok=0} if z0b!=7777 {t2ok=0} 42 if t2ok==1 { pass=pass+1; gw(" [PASS] " as *u8) } else { gw(" [FAIL] " as *u8) } 43 gw("T2 address 0 held NONZERO " as *u8); gn(z0); gw(" (a register file would read 0 here), and re-wrote to " as *u8); gn(z0b); gw("\n" as *u8) 44 45 // T3: never-brick 46 let p1: i64=ram_read(R,W,AB,kind,init,src,pi,co,q,po,2); let p2: i64=ram_read(R,W,AB,kind,init,src,pi,co,q,po,2) 47 total=total+1; if p1==p2 { pass=pass+1; gw(" [PASS] " as *u8) } else { gw(" [FAIL] " as *u8) } 48 gw("T3 never-brick (#26): deterministic read, bounded tick, caller-owned state, zero hardware-state writes\n" as *u8) 49 50 // T4: liar-kill -- corrupt word-0's entire D-feed MUX, then write+read address 0; the readback must diverge 51 let DBASE: i64 = R*W + 1 + 2*R // Dmux[0][0] index (matches the lib's cell plan) 52 var ci: i64 = 0 53 while ci < W { init[DBASE + ci] = init[DBASE + ci] ^ 0xffff; ci = ci + 1 } 54 z=0; while z<nc { q[z]=0; z=z+1 } 55 ram_write(R,W,AB,kind,init,src,pi,co,q,0,12345) 56 let bad: i64 = ram_read(R,W,AB,kind,init,src,pi,co,q,po,0) 57 total=total+1; if bad != 12345 { pass=pass+1; gw(" [PASS] " as *u8) } else { gw(" [FAIL] " as *u8) } 58 gw("T4 liar-kill: corrupting word-0's D-feed MUX -> address-0 readback=" as *u8); gn(bad); gw(" != written 12345\n" as *u8) 59 60 gw("\n=== nx_fpga_ram_gate " as *u8); gn(pass); gw("/" as *u8); gn(total) 61 if pass == total { gw(" GREEN (a true RAM fabric: every address incl 0 reads back what was written -- the memory primitive for fetch-from-memory)\n" as *u8); sys_exit(0); return 0 } 62 gw(" RED\n" as *u8); sys_exit(1); return 1 63}