`nx_fpga_ram.nx` source

↩ module page · 138 lines · 5831 B
1// nx_fpga_ram.nx -- LIB: RUNG 17 -- a true RAM fabric on the SEQUENTIAL fabric. Same structure as the register file
2// (nx_fpga_regfile) -- R words x W bits of DFF state, an addressed clocked WRITE port + an addressed combinational
3// READ port, LUT4 address decode -- BUT with NO hardwired address: EVERY word (including address 0) is writable and
4// reads back what was written. That is the difference between a register file (x0 must read 0) and a memory (word 0
5// is just a word). This is what lets data live at address 0 AND lets instructions be FETCHED from a memory fabric.
6//
7// PIs (npi = 2*AB + W + 1): raddr[0..AB-1] | waddr[AB..2AB-1] | wdata[2AB..2AB+W-1] | we[2AB+W].
8// NEVER-BRICK (#26): bounded state (caller-owned q[]), bounded tick, deterministic, no hardware write.
9// license_tier: ORIGINAL
10import "nx_fpga_seq.nx"
11import "nx_fpga_lut.nx"
12import "nx_fpga_fabric.nx"
13import "nx_syscalls.nx"
14
15func ram_addr_inputs(src: *i64, cell: i64, addr0_pi: i64, ab: i64, const0_src: i64) -> i64 {
  var j: i64 = 0
  while j < 4 {
      if j < ab { src[cell*4+j] = addr0_pi + j } else { src[cell*4+j] = const0_src }
      j = j + 1
  }
  return 0
22}
23
24func seq_build_ram(R: i64, W: i64, AB: i64, kind: *i64, init: *i64, src: *i64, po_src: *i64) -> i64 {
  let npi: i64 = 2*AB + W + 1
  let RADDR0: i64 = 0
  let WADDR0: i64 = AB
  let WDATA0: i64 = 2*AB
  let WE: i64 = 2*AB + W
  let kAND: i64 = fl_gate_to_lut4(FL_AND)
  let kOR:  i64 = fl_gate_to_lut4(FL_OR)
  let kMUX: i64 = fl_gate_to_lut4(FL_MUX)
  // ---- cell-index plan (Dmux spans ALL R words, not R-1) ----
  let C0: i64 = R*W                                   // const0
  let WSEL: i64 = R*W + 1                              // wsel_r = WSEL + r
  let WRITE: i64 = WSEL + R                            // write_r = WRITE + r
  let DBASE: i64 = WRITE + R                           // Dmux[r][i] = DBASE + r*W + i  (r=0..R-1)
  let RSEL: i64 = DBASE + R*W                          // rsel_r = RSEL + r
  let GBASE: i64 = RSEL + R                            // gated[r][i] = GBASE + r*W + i
  let OBASE: i64 = GBASE + R*W                         // or[i][k] = OBASE + i*(R-1) + k  (k=0..R-2)
  let const0_src: i64 = npi + C0
42
  // const0
  kind[C0]=0; init[C0]=0; src[C0*4+0]=0; src[C0*4+1]=0; src[C0*4+2]=0; src[C0*4+3]=0
45
  // DFF cells (state) + their D wiring -- EVERY word fed by its Dmux (no x0 hardwire)
  var r: i64 = 0
  while r < R {
      var i: i64 = 0
      while i < W {
          let dff: i64 = r*W + i
          kind[dff]=1; init[dff]=0
          src[dff*4+0] = npi + (DBASE + r*W + i)
          src[dff*4+1]=0; src[dff*4+2]=0; src[dff*4+3]=0
          i = i + 1
      }
      r = r + 1
  }
  // write decode: wsel_r = (waddr==r), write_r = wsel_r AND we
  r = 0
  while r < R {
      let ws: i64 = WSEL + r
      kind[ws]=0; init[ws]=(1 << r); ram_addr_inputs(src, ws, WADDR0, AB, const0_src)
      let wr: i64 = WRITE + r
      kind[wr]=0; init[wr]=kAND; src[wr*4+0]=npi+ws; src[wr*4+1]=WE; src[wr*4+2]=npi+ws; src[wr*4+3]=npi+ws
      r = r + 1
  }
  // D-feed MUX for ALL r=0..R-1: Dmux[r][i] = write_r ? wdata_i : word[r][i]
  r = 0
  while r < R {
      var i: i64 = 0
      while i < W {
          let dm: i64 = DBASE + r*W + i
          kind[dm]=0; init[dm]=kMUX
          src[dm*4+0]=npi+(WRITE+r); src[dm*4+1]=npi+(r*W+i); src[dm*4+2]=WDATA0+i; src[dm*4+3]=npi+(r*W+i)
          i = i + 1
      }
      r = r + 1
  }
  // read: rsel_r = (raddr==r); gated[r][i] = rsel_r AND word[r][i]; out_i = OR over r
  r = 0
  while r < R {
      let rs: i64 = RSEL + r
      kind[rs]=0; init[rs]=(1 << r); ram_addr_inputs(src, rs, RADDR0, AB, const0_src)
      var i: i64 = 0
      while i < W {
          let g: i64 = GBASE + r*W + i
          kind[g]=0; init[g]=kAND; src[g*4+0]=npi+rs; src[g*4+1]=npi+(r*W+i); src[g*4+2]=npi+rs; src[g*4+3]=npi+rs
          i = i + 1
      }
      r = r + 1
  }
  // OR-reduce per bit
  var i: i64 = 0
  while i < W {
      var k: i64 = 0
      while k < R - 1 {
          let oc: i64 = OBASE + i*(R-1) + k
          kind[oc]=0; init[oc]=kOR
          var in0: i64 = npi + (GBASE + 0*W + i)
          if k > 0 { in0 = npi + (OBASE + i*(R-1) + k - 1) }
          let in1: i64 = npi + (GBASE + (k+1)*W + i)
          src[oc*4+0]=in0; src[oc*4+1]=in1; src[oc*4+2]=in0; src[oc*4+3]=in0
          k = k + 1
      }
      po_src[i] = npi + (OBASE + i*(R-1) + (R-2))
      i = i + 1
  }
  return npi
110}
111
112// total cell count for an R x W RAM (Dmux now spans R words, not R-1)
113func ram_ncells(R: i64, W: i64) -> i64 { return (R*W) + 1 + R + R + R*W + R + R*W + W*(R-1) }
114
115// WRITE word[addr] = val on a clock tick (we=1). raddr idle.
116func ram_write(R: i64, W: i64, AB: i64, kind: *i64, init: *i64, src: *i64, pi: *i64, cellout: *i64, q: *i64, addr: i64, val: i64) -> i64 {
  var j: i64 = 0
  while j < AB { pi[j] = 0; pi[AB+j] = (addr >> j) & 1; j = j + 1 }
  var i: i64 = 0
  while i < W { pi[2*AB + i] = (val >> i) & 1; i = i + 1 }
  pi[2*AB + W] = 1
  seq_tick(ram_ncells(R, W), 2*AB + W + 1, kind, init, src, pi, cellout, q)
  return 0
124}
125
126// READ word[addr] combinationally (no tick; we=0).
127func ram_read(R: i64, W: i64, AB: i64, kind: *i64, init: *i64, src: *i64, pi: *i64, cellout: *i64, q: *i64, po_src: *i64, addr: i64) -> i64 {
  var j: i64 = 0
  while j < AB { pi[j] = (addr >> j) & 1; pi[AB+j] = 0; j = j + 1 }
  var i: i64 = 0
  while i < W { pi[2*AB + i] = 0; i = i + 1 }
  pi[2*AB + W] = 0
  seq_eval(ram_ncells(R, W), 2*AB + W + 1, kind, init, src, pi, cellout, q)
  var s: i64 = 0
  i = 0
  while i < W { s = s | ((fab_po(po_src[i], 2*AB + W + 1, pi, cellout) & 1) << i); i = i + 1 }
  return s
138}
nx_fpga_ram.nx source

`nx_fpga_ram.nx` source
