code wiki / _hdl_build / nx_fpga_addsub_gate.nx

nx_fpga_addsub_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_addsub_gate.nx

7609 B150 linesdepth 6pulls 8 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 4 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_addsub.nx nx_syscalls.nx nx_fpga_addsub_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_addsub.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap fab_build_addsub fab_parity3_init fab_maj3_init fl_gate_to_lut4 fl_gate_ref lut4_index fab_addsub_run fab_eval fab_resolve lut4_eval lut4_index ↻ fab_po fab_resolve ↻ native_addsub gn sys_exit

structs

none

consts

none

functions

15func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
18func native_addsub(a: i64, b: i64, sub: i64, mask: i64) -> i64
23func main() -> i64