code wiki / _hdl_build / nx_fpga_bitstream_gate.nx

nx_fpga_bitstream_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_bitstream_gate.nx

6260 B112 linesdepth 5pulls 5 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

about

nx_fpga_bitstream_gate.nx -- GATE for the sovereign bitstream encoder (M4 prjtrellis replacement). Encodes a real fabric (the full-adder: SUM=parity3, COUT=maj3) and proves the bitstream is a faithful, loadable twin: T1 STRUCTURAL RT -- encode->decode reconstructs inits/routing/outputs byte-exact (consumed == size). T2 FUNCTIONAL RT -- the DECODED fabric run on fab_eval == the golden full-adder over all 8 input combos (a loaded bitstream computes the design exactly). T3 FORMAT SIZE -- packed size == 4 (magic) + 6 (hdr) + 2 cells*10 + 2 outs*2 = 34 bytes. T4 LIAR-KILL -- flipping ONE bitstream byte makes the decoded fabric compute the WRONG answer (the bits are load-bearing). T5 NEVER-BRICK -- deterministic (re-encode byte-identical); writes knowledge/nx_fpga.nbit (the sovereign .bit). GREEN iff all pass. Sovereign nx_cc->nxasm, no Lattice/prjtrellis/Verilog. expect_exit: 0 license_tier: ORIGINAL

dependencies 4 imports · 0 importers

nx_fpga_bitstream.nx nx_fpga_fabric.nx nx_fpga_lut.nx nx_syscalls.nx nx_fpga_bitstream_gate.nx

imports: nx_fpga_bitstream.nxnx_fpga_fabric.nxnx_fpga_lut.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main w sys_write sys_mmap parity3_init maj3_init bs_encode bs_put16 wn w ↻ sys_mmap ↻ sys_write ↻ bs_decode bs_get16 fab_eval fab_resolve lut4_eval lut4_index fab_po fab_resolve ↻ bs_write sys_openat_wr sys_write ↻ sys_close sys_exit

structs

none

consts

none

functions

15func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: wnmain calls 1: sys_write
16func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
called by 1: main calls 3: wsys_mmapsys_write
17func parity3_init() -> i64 { var tt: i64=0; var i: i64=0; while i<16 { let a: i64=i&1; let b: i64=(i>>1)&1; let c: i64=(i>>2)&1; if (a^b^c)==1 { tt=tt|(1<<i) } i=i+1 } return tt }
called by 1: main
18func maj3_init() -> i64 { var tt: i64=0; var i: i64=0; while i<16 { let a: i64=i&1; let b: i64=(i>>1)&1; let c: i64=(i>>2)&1; if (a+b+c)>=2 { tt=tt|(1<<i) } i=i+1 } return tt }
called by 1: main
20func main() -> i64