code wiki / _hdl_build / nx_fpga_bitstream.nx
nx_fpga_bitstream.nx
buildroot/runtime/_hdl_build/nx_fpga_bitstream.nx
about
nx_fpga_bitstream.nx -- LIB: sovereign BITSTREAM ENCODER (omniforge SI M4 = the prjtrellis replacement, no Lattice
tools). After place-and-route, the fabric configuration (per-cell LUT init + the routing wire-sources + primary
outputs) is serialized into a packed BINARY bitstream -- the bits that load onto the fabric to make it compute the
circuit. The twin property: encode -> decode -> run on fab_eval reproduces the design EXACTLY (a loaded bitstream
behaves like the design). Decodes back too (round-trip), and writes a real .nbit file (the bridge to JTAG + a
physical boot). Format: "NBIT" magic, u16 {ncells,npi,npo}, per cell {init,4x src} u16, then npo x po_src u16.
never-brick #26: pure memory + a file write (no hardware), bounded, deterministic. license_tier: ORIGINAL
dependencies 2 imports · 2 importers
imports: nx_fpga_fabric.nxnx_syscalls.nx
imported by: nx_fpga_bitstream_gate.nxnx_jtag_load_gate.nx
structs
| none |
consts
| 10 | const K_MAGIC_65535: i64 = 65535 |
functions
| 12 | func bs_put16(buf: *u8, pos: i64, v: i64) -> i64 called by 1: bs_encode |
| 17 | func bs_get16(buf: *u8, pos: i64) -> i64 called by 1: bs_decode |
| 22 | func bs_encode(inits: *i64, src: *i64, po_src: *i64, ncells: i64, npi: i64, npo: i64, buf: *u8) -> i64 |
| 44 | func bs_decode(buf: *u8, inits_out: *i64, src_out: *i64, po_out: *i64, hdr_out: *i64) -> i64 |
| 67 | func bs_write(path: *u8, buf: *u8, size: i64) -> i64 |