code wiki / _hdl_build / nx_jtag_load_gate.nx
nx_jtag_load_gate.nx
buildroot/runtime/_hdl_build/nx_jtag_load_gate.nx
about
nx_jtag_load_gate.nx -- GATE for the JTAG bitstream loader (M5 OpenOCD replacement). Loads the full-adder bitstream
through a faithful IEEE 1149.1 TAP and proves the load is real:
T1 PROTOCOL -- driving the TAP reaches Update-DR (state 8) and shifts all 272 bits.
T2 FAITHFUL -- the shifted-in config Data Register == the bitstream bits (no loss).
T3 CONFIGURED -- reassemble -> decode the loaded bits -> the fabric runs the golden full-adder (config works).
T4 LIAR-KILL -- a wrong TMS sequence (never reaches Shift-DR) shifts 0 bits (you must speak the real protocol).
T5 NEVER-BRICK-- volatile config, deterministic re-load, bounded.
GREEN iff all pass. Sovereign nx_cc->nxasm, no OpenOCD/Lattice. expect_exit: 0 license_tier: ORIGINAL
dependencies 5 imports · 0 importers
imports: nx_jtag_load.nxnx_fpga_bitstream.nxnx_fpga_fabric.nxnx_fpga_lut.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 15 | func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 16 | func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 17 | func parity3_init() -> i64 { var tt: i64=0; var i: i64=0; while i<16 { let a: i64=i&1; let b: i64=(i>>1)&1; let c: i64=(i>>2)&1; if (a^b^c)==1 { tt=tt|(1<<i) } i=i+1 } return tt } called by 1: main |
| 18 | func maj3_init() -> i64 { var tt: i64=0; var i: i64=0; while i<16 { let a: i64=i&1; let b: i64=(i>>1)&1; let c: i64=(i>>2)&1; if (a+b+c)>=2 { tt=tt|(1<<i) } i=i+1 } return tt } called by 1: main |
| 20 | func main() -> i64 |