code wiki / _hdl_build / nx_jtag_load.nx

nx_jtag_load.nx

buildroot/runtime/_hdl_build/nx_jtag_load.nx

2866 B59 linesdepth 2pulls 2 transitivereach 1 importersview sourcekind library
docsdependenciesstructsconstsfunctions

about

nx_jtag_load.nx -- LIB: JTAG bitstream LOADER (omniforge SI M5 = the OpenOCD replacement, sim). Models the REAL IEEE 1149.1 TAP state machine (16 states, TMS-driven) and loads a bitstream into a config Data Register via Shift-DR -> Update-DR -- exactly how OpenOCD drives an FPGA. The twin property: the bits shifted in arrive in config faithfully, and the configured fabric runs the design. never-brick #26: VOLATILE config (an SRAM model, no persistent/flash write -> a power cycle clears it, can't brick BY CONSTRUCTION), bounded, deterministic. license_tier: ORIGINAL

dependencies 1 imports · 1 importers

nx_syscalls.nx nx_jtag_load.nx nx_jtag_load_gate.nx

imports: nx_syscalls.nx

imported by: nx_jtag_load_gate.nx

structs

none

consts

none

functions

10func tap_next(state: i64, tms: i64) -> i64
called by 1: jtag_run
31func jtag_run(tms: *i64, tdi: *i64, nclk: i64, dr_out: *i64, shifted_out: *i64) -> i64
called by 1: main calls 1: tap_next
45func jtag_build_load(nbits: i64, bits: *i64, tms: *i64, tdi: *i64) -> i64
called by 1: main