nx_fpga_regfile.nx

nx_fpga_regfile.nx -- LIB: RUNG 10 -- a REGISTER FILE on the SEQUENTIAL fabric (the core CPU storage). R registers x W bits of DFF state; an addressed WRITE port (waddr,wdata,we -- clocked: reg[waddr]<-wdata on TICK iff we) and an addressed combinational READ port (raddr -> reg[raddr]). Register 0 (x0) is HARDWIRED to 0 (its DFF D = const0; always reads 0). Address decode = ONE LUT4 per register (init 1<<r over the addr bits, unused LUT pins tied to const0) -- works for R<=16 (AB<=4); R=32 needs a 2-level decode (a follow-on). Read = decode-then-gated-OR (exactly one register selected). Built on nx_fpga_seq (DFF + seq_tick) + nx_fpga_lut. PIs (npi = 2*AB + W + 1): raddr[0..AB-1] | waddr[AB..2AB-1] | wdata[2AB..2AB+W-1] | we[2AB+W]. NEVER-BRICK (#26): bounded state (caller-owned q[]), bounded tick, deterministic, x0 invariant, no hw write. license_tier: ORIGINAL